Handle the following architectures in generic flashrom code
- x86/x86_64 (little endian)
- PowerPC (big endian)
- MIPS (big+little endian)
No changes to programmer specific code. This means any drivers with MMIO
access will _not_ suddenly start working on big endian systems, but with
this patch everything is in place to fix them.
Compilation should work on all architectures listed above for all
drivers except nic3com and nicrealtek which require PCI Port IO which is
x86-only for now.
To compile without nic3com and nicrealtek, run
make distclean
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no
Thanks to Misha Manulis for testing early versions of this patch on
PowerPC (big endian) with the satasii programmer.
Thanks to Segher Boessenkool for design review and for helping out with
compiler tricks and pointing out that we need eieio on PowerPC.
Thanks to Vladimir Serbinenko for compile testing on MIPS (little
endian) and PowerPC (big endian) and for runtime testing on MIPS (little
endian).
Thanks to David Daney for compile testing on MIPS (big endian).
Thanks to Uwe Hermann for compile and runtime testing on x86_64.
DO NOT RUN flashrom ON NON-X86 AFTER APPLYING THIS PATCH!
This patch only provides the infrastructure, but does not convert any
drivers, so flashrom will compile, but it won't do the right thing on
non-x86 platforms.
Corresponding to flashrom svn r1013.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Misha Manulis <misha@manulis.com>
Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
diff --git a/Makefile b/Makefile
index dff5e91..59fd686 100644
--- a/Makefile
+++ b/Makefile
@@ -124,7 +124,9 @@
ifeq ($(CONFIG_INTERNAL), yes)
FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
NEED_PCI := yes
endif
@@ -260,7 +262,7 @@
rm -f .dependencies .features .libdeps
dep:
- @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+ @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies
strip: $(PROGRAM)
$(STRIP) $(STRIP_ARGS) $(PROGRAM)
diff --git a/board_enable.c b/board_enable.c
index ddb6669..4251601 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -28,6 +28,7 @@
#include <fcntl.h>
#include "flash.h"
+#if defined(__i386__) || defined(__x86_64__)
/*
* Helper functions for many Winbond Super I/Os of the W836xx range.
*/
@@ -1348,6 +1349,8 @@
return it8712f_gpio_set(32, 1);
}
+#endif
+
/**
* Below is the list of boards which need a special "board enable" code in
* flashrom before their ROM chip can be accessed/written to.
@@ -1391,6 +1394,7 @@
struct board_pciid_enable board_pciid_enables[] = {
/* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
{0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
{0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},
{0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
@@ -1458,7 +1462,7 @@
{0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
{0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
-
+#endif
{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
};
diff --git a/chipset_enable.c b/chipset_enable.c
index 33ba2ba..76893a1 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -34,6 +34,8 @@
#include <fcntl.h>
#include "flash.h"
+#if defined(__i386__) || defined(__x86_64__)
+
extern int ichspi_lock;
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
return 0;
}
+#endif
+
/* Please keep this list alphabetically sorted by vendor/device. */
const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
{0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
{0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
{0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
@@ -1425,7 +1430,7 @@
{0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
{0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
{0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
-
+#endif
{},
};
diff --git a/flash.h b/flash.h
index 436a1fe..a201af3 100644
--- a/flash.h
+++ b/flash.h
@@ -63,8 +63,10 @@
PROGRAMMER_ATAHPT,
#endif
#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
PROGRAMMER_IT87SPI,
#endif
+#endif
#if FT2232_SPI_SUPPORT == 1
PROGRAMMER_FT2232SPI,
#endif
@@ -407,6 +409,12 @@
uint8_t mmio_readb(void *addr);
uint16_t mmio_readw(void *addr);
uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);
/* programmer.c */
int noop_shutdown(void);
@@ -603,6 +611,7 @@
enum spi_controller {
SPI_CONTROLLER_NONE,
#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
SPI_CONTROLLER_ICH7,
SPI_CONTROLLER_ICH9,
SPI_CONTROLLER_IT87XX,
@@ -610,6 +619,7 @@
SPI_CONTROLLER_VIA,
SPI_CONTROLLER_WBSIO,
#endif
+#endif
#if FT2232_SPI_SUPPORT == 1
SPI_CONTROLLER_FT2232,
#endif
diff --git a/flashrom.c b/flashrom.c
index 99b8da5..3cf55e6 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -276,6 +276,7 @@
#endif
#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
{
.name = "it87spi",
.init = it87spi_init,
@@ -293,6 +294,7 @@
.delay = internal_delay,
},
#endif
+#endif
#if FT2232_SPI_SUPPORT == 1
{
@@ -1208,16 +1210,21 @@
#endif
#endif
#ifdef __clang__
- msg_ginfo(" LLVM %i/clang %i", __llvm__, __clang__);
+ msg_ginfo(" LLVM %i/clang %i, ", __llvm__, __clang__);
#elif defined(__GNUC__)
msg_ginfo(" GCC");
#ifdef __VERSION__
- msg_ginfo(" %s", __VERSION__);
+ msg_ginfo(" %s,", __VERSION__);
#else
- msg_ginfo(" unknown version");
+ msg_ginfo(" unknown version,");
#endif
#else
- msg_ginfo(" unknown compiler");
+ msg_ginfo(" unknown compiler,");
+#endif
+#if defined (__FLASHROM_LITTLE_ENDIAN__)
+ msg_ginfo(" little endian");
+#else
+ msg_ginfo(" big endian");
#endif
msg_ginfo("\n");
}
diff --git a/hwaccess.c b/hwaccess.c
index 830013e..44d7871 100644
--- a/hwaccess.c
+++ b/hwaccess.c
@@ -26,6 +26,15 @@
#include <errno.h>
#include "flash.h"
+#if defined(__i386__) || defined(__x86_64__)
+
+/* sync primitive is not needed because x86 uses uncached accesses
+ * which have a strongly ordered memory model.
+ */
+static inline void sync_primitive(void)
+{
+}
+
#if defined(__FreeBSD__) || defined(__DragonFly__)
int io_fd;
#endif
@@ -54,19 +63,68 @@
#endif
}
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+static inline void sync_primitive(void)
+{
+ /* Prevent reordering and/or merging of reads/writes to hardware.
+ * Such reordering and/or merging would break device accesses which
+ * depend on the exact access order.
+ */
+ asm("eieio" : : : "memory");
+}
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+void get_io_perms(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+void release_io_perms(void)
+{
+}
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses
+ * in mode 2 which has a strongly ordered memory model.
+ */
+static inline void sync_primitive(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on MIPS. */
+void get_io_perms(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on MIPS. */
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
void mmio_writeb(uint8_t val, void *addr)
{
*(volatile uint8_t *) addr = val;
+ sync_primitive();
}
void mmio_writew(uint16_t val, void *addr)
{
*(volatile uint16_t *) addr = val;
+ sync_primitive();
}
void mmio_writel(uint32_t val, void *addr)
{
*(volatile uint32_t *) addr = val;
+ sync_primitive();
}
uint8_t mmio_readb(void *addr)
@@ -83,3 +141,33 @@
{
return *(volatile uint32_t *) addr;
}
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+ mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+ mmio_writew(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+ mmio_writel(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+ return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+ return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+ return le_to_cpu32(mmio_readl(addr));
+}
diff --git a/hwaccess.h b/hwaccess.h
index 7a76925..91366a6 100644
--- a/hwaccess.h
+++ b/hwaccess.h
@@ -24,13 +24,139 @@
#ifndef __HWACCESS_H__
#define __HWACCESS_H__ 1
+#if defined (__i386__) || defined (__x86_64__)
#if defined(__GLIBC__)
#include <sys/io.h>
#endif
+#endif
+
#if NEED_PCI == 1
#include <pci/pci.h>
#endif
+#if defined (__i386__) || defined (__x86_64__)
+
+/* All x86 is little-endian. */
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* MIPS can be either endian. */
+#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL)
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB)
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PowerPC can be either endian. */
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+#define __FLASHROM_BIG_ENDIAN__ 1
+/* Error checking in case some weird header has #defines for LE as well. */
+#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__)
+#error Conflicting endianness #define
+#endif
+#else
+#error Little-endian PowerPC #defines are unknown
+#endif
+
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+/* Nonstandard libc-specific macros for determining endianness. */
+#if defined(__GLIBC__)
+#include <endian.h>
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif BYTE_ORDER == BIG_ENDIAN
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+#endif
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+#error Unable to determine endianness. Please add support for your arch or libc.
+#endif
+
+#define ___constant_swab8(x) ((uint8_t) ( \
+ (((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t) ( \
+ (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \
+ (((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t) ( \
+ (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
+ (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
+ (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \
+ (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t) ( \
+ (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \
+ (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \
+ (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \
+ (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \
+ (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \
+ (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \
+ (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \
+ (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (__FLASHROM_BIG_ENDIAN__)
+
+#define cpu_to_le(bits) \
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \
+{ \
+ return ___constant_swab##bits(val); \
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#elif defined (__FLASHROM_LITTLE_ENDIAN__)
+
+#define cpu_to_be(bits) \
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \
+{ \
+ return ___constant_swab##bits(val); \
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#else
+
+#error Could not determine endianness.
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
+#define __FLASHROM_HAVE_OUTB__ 1
+
/* for iopl and outb under Solaris */
#if defined (__sun) && (defined(__i386) || defined(__amd64))
#include <strings.h>
@@ -162,4 +288,18 @@
int freebsd_wrmsr(int addr, msr_t msr);
#endif
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* PCI port I/O is not yet implemented on MIPS. */
+
+#else
+
+#error Unknown architecture, please check if it supports PCI port IO.
+
+#endif
+
#endif /* !__HWACCESS_H__ */
diff --git a/ichspi.c b/ichspi.c
index 8add13e..e9a3611 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -33,6 +33,8 @@
*
*/
+#if defined(__i386__) || defined(__x86_64__)
+
#include <string.h>
#include "flash.h"
#include "chipdrivers.h"
@@ -832,3 +834,5 @@
}
return ret;
}
+
+#endif
diff --git a/internal.c b/internal.c
index 174370c..bbad788 100644
--- a/internal.c
+++ b/internal.c
@@ -99,10 +99,12 @@
#endif
#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
int force_boardenable = 0;
int force_boardmismatch = 0;
+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
void probe_superio(void)
{
superio = probe_superio_ite();
@@ -112,8 +114,9 @@
superio = probe_superio_winbond();
#endif
}
+#endif
-int is_laptop;
+int is_laptop = 0;
int internal_init(void)
{
@@ -166,10 +169,13 @@
* mainboard specific flash enable sequence.
*/
coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
dmi_init();
/* Probe for the Super I/O chip and fill global struct superio. */
probe_superio();
+#endif
/* Warn if a laptop is detected. */
if (is_laptop) {
@@ -203,8 +209,10 @@
"will most likely fail.\n");
}
+#if defined(__i386__) || defined(__x86_64__)
/* Probe for IT87* LPC->SPI translation unconditionally. */
it87xx_probe_spi_flash(NULL);
+#endif
board_flash_enable(lb_vendor, lb_part);
diff --git a/it87spi.c b/it87spi.c
index 0ee7d12..4f413ba 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -23,6 +23,8 @@
* Contains the ITE IT87* SPI specific routines
*/
+#if defined(__i386__) || defined(__x86_64__)
+
#include <string.h>
#include <stdlib.h>
#include "flash.h"
@@ -351,3 +353,5 @@
return 0;
}
+
+#endif
diff --git a/nic3com.c b/nic3com.c
index d3dcce5..8064b57 100644
--- a/nic3com.c
+++ b/nic3com.c
@@ -18,6 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#if defined(__i386__) || defined(__x86_64__)
+
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
@@ -112,3 +114,7 @@
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
return INB(io_base_addr + BIOS_ROM_DATA);
}
+
+#else
+#error PCI port I/O access is not supported on this architecture yet.
+#endif
diff --git a/nicrealtek.c b/nicrealtek.c
index 80291f1..d145886 100644
--- a/nicrealtek.c
+++ b/nicrealtek.c
@@ -18,6 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#if defined(__i386__) || defined(__x86_64__)
+
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
@@ -93,3 +95,7 @@
return val;
}
+
+#else
+#error PCI port I/O access is not supported on this architecture yet.
+#endif
diff --git a/physmap.c b/physmap.c
index 03fef95..1f47ce0 100644
--- a/physmap.c
+++ b/physmap.c
@@ -241,6 +241,8 @@
return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
}
+#if defined(__i386__) || defined(__x86_64__)
+
#ifdef __linux__
/*
* Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -462,4 +464,6 @@
#endif
#endif
#endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
diff --git a/print.c b/print.c
index 4d91d33..a8da65f 100644
--- a/print.c
+++ b/print.c
@@ -261,6 +261,7 @@
/* Please keep this list alphabetically ordered by vendor/board. */
const struct board_info boards_ok[] = {
/* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
{ "Abit", "AX8", },
{ "Abit", "Fatal1ty F-I90HD", },
{ "Advantech", "PCM-5820", },
@@ -381,13 +382,14 @@
{ "VIA", "pc2500e", },
{ "VIA", "PC3500G", },
{ "VIA", "VB700X", },
-
+#endif
{},
};
/* Please keep this list alphabetically ordered by vendor/board. */
const struct board_info boards_bad[] = {
/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
{ "Abit", "IS-10", },
{ "ASRock", "K7VT4A+", },
{ "ASUS", "MEW-AM", },
@@ -405,29 +407,31 @@
{ "Sun", "Fire x4200", },
{ "Sun", "Fire x4540", },
{ "Sun", "Fire x4600", },
-
+#endif
{},
};
/* Please keep this list alphabetically ordered by vendor/board. */
const struct board_info laptops_ok[] = {
/* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
{ "Lenovo", "3000 V100 TF05Cxx", },
{ "Acer", "Aspire 1520", },
-
+#endif
{},
};
/* Please keep this list alphabetically ordered by vendor/board. */
const struct board_info laptops_bad[] = {
/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
{ "Acer", "Aspire One", },
{ "ASUS", "Eee PC 701 4G", },
{ "Dell", "Latitude CPi A366XT", },
{ "HP/Compaq", "nx9010", },
{ "IBM/Lenovo", "Thinkpad T40p", },
{ "IBM/Lenovo", "240", },
-
+#endif
{},
};
#endif
diff --git a/print_wiki.c b/print_wiki.c
index 4d7f3ef..3d51bfa 100644
--- a/print_wiki.c
+++ b/print_wiki.c
@@ -104,6 +104,7 @@
/* Please keep these lists alphabetically ordered by vendor/board. */
const struct board_info_url boards_url[] = {
/* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
{ "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y&fMTYPE=Socket%20939&pMODEL_NAME=AX8" },
{ "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAME=Fatal1ty+F-I90HD&fMTYPE=LGA775" },
{ "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" },
@@ -279,8 +280,10 @@
{ "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&motherboard_id=221" }, /* EPIA-N link for now */
{ "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&motherboard_id=261" },
{ "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" },
+#endif
/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
{ "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAME=IS-10&fMTYPE=Socket+478" },
{ "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" },
{ "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" },
@@ -298,18 +301,23 @@
{ "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" },
{ "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" },
{ "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" },
+#endif
/* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
{ "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire1520nv.shtml" },
{ "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3000Notebook&series=Lenovo+3000+V+Series#viewallmodelstop" },
+#endif
/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
{ "Acer", "Aspire One", NULL },
{ "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" },
{ "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" },
{ "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c00348514" },
{ "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" },
{ "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" },
+#endif
{ NULL, NULL, 0 },
};
@@ -317,6 +325,7 @@
/* Please keep these lists alphabetically ordered by vendor/board. */
const struct board_info_notes boards_notes[] = {
/* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
{ "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." },
{ "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." },
{ "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." },
@@ -324,23 +333,30 @@
{ "BCOM", "WinNET100", "Used in the IGEL-316 thin client." },
{ "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." },
{ "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" },
+#endif
/* Verified working boards that DO need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
{ "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." },
+#endif
/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
{ "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." },
{ "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." },
+#endif
/* Verified working laptops. */
/* None which need comments, yet... */
/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
{ "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" },
{ "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." },
{ "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." },
{ "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." },
{ "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." },
+#endif
{ NULL, NULL, 0 },
};
diff --git a/sb600spi.c b/sb600spi.c
index 5fcbd9e..973d1ad 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -21,6 +21,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#if defined(__i386__) || defined(__x86_64__)
+
#include <string.h>
#include "flash.h"
#include "chipdrivers.h"
@@ -166,3 +168,5 @@
return 0;
}
+
+#endif
diff --git a/spi.c b/spi.c
index 9bb4687..24696fb 100644
--- a/spi.c
+++ b/spi.c
@@ -42,6 +42,7 @@
},
#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
{ /* SPI_CONTROLLER_ICH7 */
.command = ich_spi_send_command,
.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
.write_256 = wbsio_spi_write_1,
},
#endif
+#endif
#if FT2232_SPI_SUPPORT == 1
{ /* SPI_CONTROLLER_FT2232 */
diff --git a/spi25.c b/spi25.c
index 5a52f28..b45faf8 100644
--- a/spi25.c
+++ b/spi25.c
@@ -172,12 +172,14 @@
/* only some SPI chipsets support 4 bytes commands */
switch (spi_controller) {
#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_ICH9:
case SPI_CONTROLLER_VIA:
case SPI_CONTROLLER_SB600:
case SPI_CONTROLLER_WBSIO:
#endif
+#endif
#if FT2232_SPI_SUPPORT == 1
case SPI_CONTROLLER_FT2232:
#endif
@@ -996,11 +998,13 @@
switch (spi_controller) {
#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
case SPI_CONTROLLER_WBSIO:
msg_cerr("%s: impossible with Winbond SPI masters,"
" degrading to byte program\n", __func__);
return spi_chip_write_1(flash, buf);
#endif
+#endif
default:
break;
}
diff --git a/wbsio_spi.c b/wbsio_spi.c
index ca39322..d733247 100644
--- a/wbsio_spi.c
+++ b/wbsio_spi.c
@@ -18,6 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#if defined(__i386__) || defined(__x86_64__)
+
#include <string.h>
#include "flash.h"
#include "chipdrivers.h"
@@ -199,3 +201,5 @@
return spi_chip_write_1(flash, buf);
}
+
+#endif