)]}'
{
  "commit": "ccae68ac91b00eb68adf11fa88e6d9a1aaa01b0b",
  "tree": "3f1f0c9d24adb8b3034dd5414b84a06b15084637",
  "parents": [
    "d32e18b0c03a0426f808477544f6ecec9ae10f66"
  ],
  "author": {
    "name": "Nikolai Artemiev",
    "email": "nartemiev@google.com",
    "time": "Tue Mar 08 01:07:01 2022 +1100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Dec 30 01:16:47 2022 +0100"
  },
  "message": "writeprotect.c: refactor and fix wp_mode functions\n\nThis is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07.\n\nUse a lookup table in get_wp_mode() and drop the srp_bit_present check,\nsince a chip without SRP is just FLASHROM_WP_MODE_DISABLED.\n\nAdd a srp_bit_present check to set_wp_mode() if the mode requires it.\n\nTested: flashrom --wp-{enable,disable,status} on AMD dut\n\nChange-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70977\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ecf471fe49f32e17567bd4601b0a417c84bdcd16",
      "old_mode": 33188,
      "old_path": "writeprotect.c",
      "new_id": "8f70a7c866cf7fd9574a8c7aef956155ecf25615",
      "new_mode": 33188,
      "new_path": "writeprotect.c"
    }
  ]
}