ft2232_spi: clarify the comment about gpio configuration
The comment explaining gpio levels might be easily misunderstood when
the reader misses the word `output`. Add an explicit description of
handling of the GPIOL* pins to avoid that and make things even more
clear.
Change-Id: Iaceec889a65ead8cdde917f61b2a9695d440f781
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57808
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71424
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/ft2232_spi.c b/ft2232_spi.c
index c70cba5..0e95590 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -91,8 +91,11 @@
* "set data bits low byte" MPSSE command that sets the initial
* state and the direction of the I/O pins. `cs_bits` pins default
* to high and will be toggled during SPI transactions. All other
- * output pins will be kept low all the time. On exit, all pins
- * will be reconfigured as inputs.
+ * output pins will be kept low all the time. For some programmers,
+ * some reserved GPIOL* pins are used as outputs. Free GPIOL* pins
+ * are configured as inputs, while it's possible to use one of them
+ * as additional CS# signal through the parameter `csgpiol`. On exit,
+ * all pins will be reconfigured as inputs.
*
* The pin offsets are as follows:
* TCK/SK is bit 0.