par_master: Fix propagation of register_par_master() return values
This patch checks return value of register_par_master()
so that in case of an error this error is not ignored anymore.
Tested: builds and ninja test
Change-Id: I377afae41708c7433a56615e2f096bce9c5349f1
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/57192
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72234
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/atahpt.c b/atahpt.c
index 0667b05..660c8f7 100644
--- a/atahpt.c
+++ b/atahpt.c
@@ -75,9 +75,7 @@
reg32 |= (1 << 24);
rpci_write_long(dev, REG_FLASH_ACCESS, reg32);
- register_par_master(&par_master_atahpt, BUS_PARALLEL, NULL);
-
- return 0;
+ return register_par_master(&par_master_atahpt, BUS_PARALLEL, NULL);
}
static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
diff --git a/atapromise.c b/atapromise.c
index 881f5f1..180551b 100644
--- a/atapromise.c
+++ b/atapromise.c
@@ -140,14 +140,13 @@
}
max_rom_decode.parallel = rom_size;
- register_par_master(&par_master_atapromise, BUS_PARALLEL, NULL);
msg_pwarn("Do not use this device as a generic programmer. It will leave anything outside\n"
"the first %zu kB of the flash chip in an undefined state. It works fine for the\n"
"purpose of updating the firmware of this device (padding may necessary).\n",
rom_size / 1024);
- return 0;
+ return register_par_master(&par_master_atapromise, BUS_PARALLEL, NULL);
}
static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
diff --git a/atavia.c b/atavia.c
index 28a4c4c..45593f6 100644
--- a/atavia.c
+++ b/atavia.c
@@ -160,9 +160,7 @@
return 1;
}
- register_par_master(&lpc_master_atavia, BUS_LPC, NULL);
-
- return 0;
+ return register_par_master(&lpc_master_atavia, BUS_LPC, NULL);
}
static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr)
diff --git a/drkaiser.c b/drkaiser.c
index dd2d68b..7ae73ab 100644
--- a/drkaiser.c
+++ b/drkaiser.c
@@ -77,9 +77,7 @@
return 1;
max_rom_decode.parallel = 128 * 1024;
- register_par_master(&par_master_drkaiser, BUS_PARALLEL, NULL);
-
- return 0;
+ return register_par_master(&par_master_drkaiser, BUS_PARALLEL, NULL);
}
static void drkaiser_chip_writeb(const struct flashctx *flash, uint8_t val,
diff --git a/gfxnvidia.c b/gfxnvidia.c
index ec04a94..85d6d71 100644
--- a/gfxnvidia.c
+++ b/gfxnvidia.c
@@ -104,9 +104,7 @@
/* Write/erase doesn't work. */
programmer_may_write = false;
- register_par_master(&par_master_gfxnvidia, BUS_PARALLEL, NULL);
-
- return 0;
+ return register_par_master(&par_master_gfxnvidia, BUS_PARALLEL, NULL);
}
static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
diff --git a/it8212.c b/it8212.c
index 2e8af86..805582b 100644
--- a/it8212.c
+++ b/it8212.c
@@ -67,8 +67,7 @@
rpci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01);
max_rom_decode.parallel = IT8212_MEMMAP_SIZE;
- register_par_master(&par_master_it8212, BUS_PARALLEL, NULL);
- return 0;
+ return register_par_master(&par_master_it8212, BUS_PARALLEL, NULL);
}
static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
diff --git a/nicintel.c b/nicintel.c
index 50dbfb5..b3f24a3 100644
--- a/nicintel.c
+++ b/nicintel.c
@@ -99,9 +99,7 @@
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
- register_par_master(&par_master_nicintel, BUS_PARALLEL, NULL);
-
- return 0;
+ return register_par_master(&par_master_nicintel, BUS_PARALLEL, NULL);
}
static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
diff --git a/nicnatsemi.c b/nicnatsemi.c
index d1d13e5..9bb2f4f 100644
--- a/nicnatsemi.c
+++ b/nicnatsemi.c
@@ -71,9 +71,7 @@
* functions below wants to be 0x0000FFFF.
*/
max_rom_decode.parallel = 131072;
- register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, NULL);
-
- return 0;
+ return register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, NULL);
}
static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
diff --git a/satamv.c b/satamv.c
index e3970d7..6d7b030 100644
--- a/satamv.c
+++ b/satamv.c
@@ -148,9 +148,7 @@
/* 512 kByte with two 8-bit latches, and
* 4 MByte with additional 3-bit latch. */
max_rom_decode.parallel = 4 * 1024 * 1024;
- register_par_master(&par_master_satamv, BUS_PARALLEL, NULL);
-
- return 0;
+ return register_par_master(&par_master_satamv, BUS_PARALLEL, NULL);
}
/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
diff --git a/satasii.c b/satasii.c
index 2c6105e..4b13e90 100644
--- a/satasii.c
+++ b/satasii.c
@@ -100,9 +100,7 @@
if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
msg_pwarn("Warning: Flash seems unconnected.\n");
- register_par_master(&par_master_satasii, BUS_PARALLEL, NULL);
-
- return 0;
+ return register_par_master(&par_master_satasii, BUS_PARALLEL, NULL);
}
static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)