diff --git a/include/flash.h b/include/flash.h
index f2a1818..3d899c7 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -186,6 +186,7 @@
 	STATUS2,
 	STATUS3,
 	SECURITY,
+	CONFIG,
 	MAX_REGISTERS
 };
 
diff --git a/include/spi.h b/include/spi.h
index 9e655fc..8935997 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -171,6 +171,11 @@
 #define JEDEC_WRSCUR_OUTSIZE	0x01
 #define JEDEC_WRSCUR_INSIZE	0x00
 
+/* Read Configuration Register */
+#define JEDEC_RDCR		0x15
+#define JEDEC_RDCR_OUTSIZE	0x01
+#define JEDEC_RDCR_INSIZE	0x01
+
 /* Enter 4-byte Address Mode */
 #define JEDEC_ENTER_4_BYTE_ADDR_MODE	0xB7
 
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 1e6a870..508ee5d 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -107,6 +107,19 @@
 		 */
 		msg_cerr("Cannot write SECURITY: unsupported by design\n");
 		return 1;
+	case CONFIG:
+		/*
+		 * This one is read via a separate command, but written as if it's SR2
+		 * in FEATURE_WRSR_EXT2 case of WRSR command.
+		 */
+		write_cmd[0] = JEDEC_WRSR;
+		if (spi_read_register(flash, STATUS1, &write_cmd[1])) {
+			msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n");
+			return 1;
+		}
+		write_cmd[2] = value;
+		write_cmd_len = 3;
+		break;
 	default:
 		msg_cerr("Cannot write register: unknown register\n");
 		return 1;
@@ -205,6 +218,9 @@
 	case SECURITY:
 		read_cmd = JEDEC_RDSCUR;
 		break;
+	case CONFIG:
+		read_cmd = JEDEC_RDCR;
+		break;
 	default:
 		msg_cerr("Cannot read register: unknown register\n");
 		return 1;