spi25_statusreg: support reading/writing configuration register
One more variation of registers.
This one is read via a separate RDCR command, but written as if it's
SR2 using WRSR_EXT2.
Ported to flashprog w/o the FEATURE_CFGR flag, we'll already have that
information in the register description.
Change-Id: I45f9afcc31f1928ef6263a749596380082963de4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Orignal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211
Orignal-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Orignal-Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/71007
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 1e6a870..508ee5d 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -107,6 +107,19 @@
*/
msg_cerr("Cannot write SECURITY: unsupported by design\n");
return 1;
+ case CONFIG:
+ /*
+ * This one is read via a separate command, but written as if it's SR2
+ * in FEATURE_WRSR_EXT2 case of WRSR command.
+ */
+ write_cmd[0] = JEDEC_WRSR;
+ if (spi_read_register(flash, STATUS1, &write_cmd[1])) {
+ msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n");
+ return 1;
+ }
+ write_cmd[2] = value;
+ write_cmd_len = 3;
+ break;
default:
msg_cerr("Cannot write register: unknown register\n");
return 1;
@@ -205,6 +218,9 @@
case SECURITY:
read_cmd = JEDEC_RDSCUR;
break;
+ case CONFIG:
+ read_cmd = JEDEC_RDCR;
+ break;
default:
msg_cerr("Cannot read register: unknown register\n");
return 1;