diff --git a/chipset_enable.c b/chipset_enable.c
index 5436493..8fdabdc 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -36,13 +36,12 @@
 unsigned long flashbase = 0;
 
 /**
- * flashrom defaults to LPC flash devices. If a known SPI controller is found
- * and the SPI strappings are set, this will be overwritten by the probing code.
- *
- * Eventually, this will become an array when multiple flash support works.
+ * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host
+ * controller is found, the init routine sets the buses_supported bitfield to
+ * contain the supported buses for that controller.
  */
 
-enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN;
+enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI;
 
 extern int ichspi_lock;
 
@@ -217,6 +216,8 @@
 	printf_debug("0x6c: 0x%04x     (CLOCK/DEBUG)\n",
 		     mmio_readw(spibar + 0x6c));
 
+	/* Not sure if it speaks all these bus protocols. */
+	buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
 	spi_controller = SPI_CONTROLLER_VIA;
 	ich_init_opcodes();
 
@@ -262,22 +263,29 @@
 	 */
 
 	if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
+		/* Not sure if it speaks LPC as well. */
+		buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
 		/* No further SPI initialization required */
 		return ret;
 	}
 
 	switch (ich_generation) {
 	case 7:
+		buses_supported = CHIP_BUSTYPE_SPI;
 		spi_controller = SPI_CONTROLLER_ICH7;
 		spibar_offset = 0x3020;
 		break;
 	case 8:
+		/* Not sure if it speaks LPC as well. */
+		buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
 		spi_controller = SPI_CONTROLLER_ICH9;
 		spibar_offset = 0x3020;
 		break;
 	case 9:
 	case 10:
 	default:		/* Future version might behave the same */
+		/* Not sure if it speaks LPC as well. */
+		buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
 		spi_controller = SPI_CONTROLLER_ICH9;
 		spibar_offset = 0x3800;
 		break;
@@ -727,8 +735,11 @@
 			has_spi = 0;
 	}
 
-	if (has_spi)
+	buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
+	if (has_spi) {
+		buses_supported |= CHIP_BUSTYPE_SPI;
 		spi_controller = SPI_CONTROLLER_SB600;
+	}
 
 	/* Read ROM strap override register. */
 	OUTB(0x8f, 0xcd6);
diff --git a/flashrom.c b/flashrom.c
index 0eb502d..c7e17d3 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -174,10 +174,51 @@
 	return 0;
 }
 
+char *strcat_realloc(char *dest, const char *src)
+{
+	dest = realloc(dest, strlen(dest) + strlen(src) + 1);
+	if (!dest)
+		return NULL;
+	strcat(dest, src);
+	return dest;
+}
+
+/* Return a string corresponding to the bustype parameter.
+ * Memory is obtained with malloc() and can be freed with free().
+ */
+char *flashbuses_to_text(enum chipbustype bustype)
+{
+	char *ret = calloc(1, 1);
+	if (bustype == CHIP_BUSTYPE_UNKNOWN) {
+		ret = strcat_realloc(ret, "Unknown,");
+	/* FIXME: Once all chipsets and flash chips have been updated, NONSPI
+	 * will cease to exist and should be eliminated here as well.
+	 */
+	} else if (bustype == CHIP_BUSTYPE_NONSPI) {
+		ret = strcat_realloc(ret, "Non-SPI,");
+	} else {
+		if (bustype & CHIP_BUSTYPE_PARALLEL)
+			ret = strcat_realloc(ret, "Parallel,");
+		if (bustype & CHIP_BUSTYPE_LPC)
+			ret = strcat_realloc(ret, "LPC,");
+		if (bustype & CHIP_BUSTYPE_FWH)
+			ret = strcat_realloc(ret, "FWH,");
+		if (bustype & CHIP_BUSTYPE_SPI)
+			ret = strcat_realloc(ret, "SPI,");
+		if (bustype == CHIP_BUSTYPE_NONE)
+			ret = strcat_realloc(ret, "None,");
+	}
+	/* Kill last comma. */
+	ret[strlen(ret) - 1] = '\0';
+	ret = realloc(ret, strlen(ret) + 1);
+	return ret;
+}
+
 struct flashchip *probe_flash(struct flashchip *first_flash, int force)
 {
 	struct flashchip *flash;
 	unsigned long base = 0, size;
+	char *tmp;
 
 	for (flash = first_flash; flash && flash->name; flash++) {
 		if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0)
@@ -188,6 +229,15 @@
 			printf_debug("failed! flashrom has no probe function for this flash chip.\n");
 			continue;
 		}
+		if (!(buses_supported & flash->bustype)) {
+			tmp = flashbuses_to_text(buses_supported);
+			printf_debug("skipped. Host bus type %s ", tmp);
+			free(tmp);
+			tmp = flashbuses_to_text(flash->bustype);
+			printf_debug("and chip bus type %s are incompatible.\n", tmp);
+			free(tmp);
+			continue;
+		}
 
 		size = flash->total_size * 1024;
 
diff --git a/it87spi.c b/it87spi.c
index d9f93e6..2528b91 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -109,14 +109,23 @@
 
 int it87spi_init(void)
 {
-	get_io_perms();
+	int ret;
 
-	return it87spi_common_init();
+	get_io_perms();
+	ret = it87spi_common_init();
+	if (!ret)
+		buses_supported = CHIP_BUSTYPE_SPI;
+	return ret;
 }
 
 int it87xx_probe_spi_flash(const char *name)
 {
-	return it87spi_common_init();
+	int ret;
+
+	ret = it87spi_common_init();
+	if (!ret)
+		buses_supported |= CHIP_BUSTYPE_SPI;
+	return ret;
 }
 
 /*
diff --git a/nic3com.c b/nic3com.c
index c6341ed..a68bd8c 100644
--- a/nic3com.c
+++ b/nic3com.c
@@ -81,6 +81,8 @@
 	 */
 	OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
 
+	buses_supported = CHIP_BUSTYPE_PARALLEL;
+
 	return 0;
 }
 
diff --git a/satasii.c b/satasii.c
index d971b24..ba211cc 100644
--- a/satasii.c
+++ b/satasii.c
@@ -67,6 +67,8 @@
 	if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
 		printf("Warning: Flash seems unconnected.\n");
 
+	buses_supported = CHIP_BUSTYPE_PARALLEL;
+
 	return 0;
 }
 
diff --git a/wbsio_spi.c b/wbsio_spi.c
index 2df5bdd..045aa0e 100644
--- a/wbsio_spi.c
+++ b/wbsio_spi.c
@@ -63,7 +63,10 @@
 			return 1;
 
 	printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
+
+	buses_supported |= CHIP_BUSTYPE_SPI;
 	spi_controller = SPI_CONTROLLER_WBSIO;
+
 	return 0;
 }