)]}'
{
  "commit": "ad55d5a4ea4bc82450b076fbf9faffc130a698bb",
  "tree": "6beb87c779785e2e3a823b171231c51c5c6f2602",
  "parents": [
    "9bb8a322e991b899a6faff4ec14d2f4c6dba447d"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.huber@secunet.com",
    "time": "Mon Jun 20 19:32:16 2022 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Dec 30 01:16:52 2022 +0100"
  },
  "message": "flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chips\n\nAccording to their datasheets, ISSI IS25LP256 and IS25WP256 support\nboth 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended\naddress register. Flashrom will use 0xc5 by default if available,\nso adding the FEATURE_4BA_EAR_1716 flag makes no difference for now\n(FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA\nset). It\u0027s better to have a comprehensive description of the chips,\nthough, in case somebody wants to use them in the future with a\nmaster that restricts available opcodes.\n\nChange-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264\nOriginal-Reviewed-by: Thomas Heijligen \u003csrc@posteo.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70994\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "267009c7122ac2a0a364d82f3abe8c4e1d13c033",
      "old_mode": 33188,
      "old_path": "flashchips.c",
      "new_id": "66b998a970ffae795c0a4dc8b687ab1459f5daf5",
      "new_mode": 33188,
      "new_path": "flashchips.c"
    }
  ]
}