)]}'
{
  "commit": "abb34fee66dc5255ac0ae770eb3d7f1c28f7b792",
  "tree": "af60db80459aba40d14cc08af031149c95ec598e",
  "parents": [
    "2bb6792361f66a78473212d4dcddfe69d7b88aad"
  ],
  "author": {
    "name": "Angel Pons",
    "email": "th3fanbus@gmail.com",
    "time": "Sun Dec 06 23:09:13 2020 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Thu Jan 05 16:07:04 2023 +0000"
  },
  "message": "chipset_enable.c: Mark Intel H110 as DEP\n\nTested reading, writing and erasing the internal flash chip using an HP\n280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled\nchipsets are marked as DEP instead of OK, this one shall also be.\n\nChange-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48384\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71333\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8e3ff92d2321f141185a09f21a4a75f9111c23dd",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "0ab8d89019a2a1b18e9cc05cd86a2d83dea4927f",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}