)]}'
{
  "commit": "aa000982f40fa68ceea7ff19d77a0d5965164525",
  "tree": "c193b049a268de3d198b4b981198b6683794152e",
  "parents": [
    "2a9e2455cd4f9b9fc5421e9b6b786a9010daf934"
  ],
  "author": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Thu Dec 17 16:20:26 2009 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Thu Dec 17 16:20:26 2009 +0000"
  },
  "message": "jedec: warn if toggle bit is stuck for too long and allow for delays between tries\n\nIf the JEDEC Toggle Bit algorithm needs more than 2^20 loops, it is a\ngood sign we should have used delays between toggle bit reads.\n\nTell the user about this. 2^20 loops need roughly a second depending on\nflash bus speed. One reason for excessive loops can be a slow operation\nlike erase.\n\nThe Winbond W39V040C requires a 50 ms delay between toggle bit reads\nduring erase according to the datasheet. Turns out a 2 ms delay is\nsufficient. Use a safety factor of 4 and default all erase operations\nto 8 ms delay between toggle reads. This is short enough not to have\na substantial negative impact on erase times, and should improve\nreliability.\n\nThis patch addresses the excessive toggle behaviour (observed on some\nnon-Winbond chips) and the toggle delay requirement (Winbond W39V040C).\n\nCorresponding to flashrom svn r807.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Javier Ortega Conde (aka Malkavian) \u003cmalkavian666@gmail.com\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8ba7b06a94d574efa45f29edd4e4a5e82d32015b",
      "old_mode": 33188,
      "old_path": "jedec.c",
      "new_id": "800d9d2250ec8df58908eca613a1b5482a649acc",
      "new_mode": 33188,
      "new_path": "jedec.c"
    }
  ]
}