)]}'
{
  "commit": "a50b8fde67fa52984980159127de789cf9a1c688",
  "tree": "cb7230f818fd01fd47e22de2258e1d6914528b74",
  "parents": [
    "291c101c66adcb1c3435934f3f49fa7f24f7c249"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.huber@secunet.com",
    "time": "Mon Mar 20 14:25:09 2017 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Mon Jun 04 10:28:53 2018 +0000"
  },
  "message": "chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs\n\nThe Kaby Lake \"200 Series\" PCHs [1,2] share the register layout of their\nSkylake \"100 Series\" siblings.\n\n[1] Intel® 200 Series (including X299) and Intel® Z370 Series\n    Chipset Families Platform Controller Hub (PCH)\n    Datasheet - Volume 1 of 2\n    Revision 003\n    Document Number 335192\n\n[2] Intel® 200 Series (including X299) Chipset Family Platform\n    Controller Hub (PCH)\n    Datasheet - Volume 2 of 2\n    Revision 003\n    Document Number 335193\n\nChange-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/26232\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "15b760ba45456039cd7abed28178621c012b65ed",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "5c874f59229bba933f42c1adc67b67bda860fb2c",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}