)]}'
{
  "commit": "a4448d9aec2c2f6122f3a2141d8ed81032fbb2e6",
  "tree": "9a784e968db73ec1e95bd27efe7aa3d7c7ca9a8e",
  "parents": [
    "d97c0e02d610485357e569b2e1662d6bc6763d9e"
  ],
  "author": {
    "name": "Michael Karcher",
    "email": "flashrom@mkarcher.dialup.fu-berlin.de",
    "time": "Thu Jul 22 18:04:15 2010 +0000"
  },
  "committer": {
    "name": "Michael Karcher",
    "email": "flashrom@mkarcher.dialup.fu-berlin.de",
    "time": "Thu Jul 22 18:04:15 2010 +0000"
  },
  "message": "Move Intel SPI initialisation to ichspi.c\n\nSmarter version could decide whether SPI is vital or not depending on\nstraps. Straps are currently implemented for ICH7. EP80579 is in the comment,\nPCH of 5 Series/3400 Series has \"LPC, reserved, PCI, SPI\".\n\nCorresponding to flashrom svn r1098.\n\nSigned-off-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "dc0e55f5221b322e8f933091bea6c6e16d6aac1a",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "bb18b4d65cd3607cf208c0e4ab2d89b099a92561",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    },
    {
      "type": "modify",
      "old_id": "ca3f6f5476893cafee68902d3eae3a05fcbc5e3d",
      "old_mode": 33188,
      "old_path": "flash.h",
      "new_id": "1cf333aca9073b5d08549a77790d1ebeaf7fb45a",
      "new_mode": 33188,
      "new_path": "flash.h"
    },
    {
      "type": "modify",
      "old_id": "d6f9118e1f33e74faadfd48aeff31033dbd06378",
      "old_mode": 33188,
      "old_path": "ichspi.c",
      "new_id": "88e993d45d4ec16f0fcf15e257dc43e297482a25",
      "new_mode": 33188,
      "new_path": "ichspi.c"
    }
  ]
}