)]}'
{
  "commit": "a319be14d4e6b9a8f01359fb3575a02d80014f66",
  "tree": "d1efc68bded2398bfbea81766793bc4853261c6a",
  "parents": [
    "d9f266d1fb83fb0f5bffe470633a7127c23cee91"
  ],
  "author": {
    "name": "Helge Wagner",
    "email": "helge.wagner@ge.com",
    "time": "Wed Aug 11 21:06:10 2010 +0000"
  },
  "committer": {
    "name": "Michael Karcher",
    "email": "flashrom@mkarcher.dialup.fu-berlin.de",
    "time": "Wed Aug 11 21:06:10 2010 +0000"
  },
  "message": "Add support for Intel 5 Series / 3400 Series chipsets\n\n(At least) for the QM57 which i have tested an additional patch was\nneeded as some reserved bits in the \"Software Sequencing Flash Control\nRegister\" (SSFC) needs to be programmed to 1 in the QM57.\n\nCorresponding to flashrom svn r1137.\n\nSigned-off-by: Helge Wagner \u003chelge.wagner@ge.com\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "05d8e09466faed3a7f02b9de535b68db796790ee",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "f191061f61f98338f662c6f025bceaf833c28cb3",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    },
    {
      "type": "modify",
      "old_id": "126ed00039ef1578e4d317e884e3582e26afb4b0",
      "old_mode": 33188,
      "old_path": "ichspi.c",
      "new_id": "bb6007e91e5604b7e2b269f10b3aa2a359843687",
      "new_mode": 33188,
      "new_path": "ichspi.c"
    }
  ]
}