)]}'
{
  "commit": "a1d6865d1ef53626a6a4ae61a89da2ba7d75f8f3",
  "tree": "cbbb97227c2ae0e4cf45b9d222e22893118f0ec0",
  "parents": [
    "9e1afb785efd0e6144a19d1faff012d4cbf5a668"
  ],
  "author": {
    "name": "Nikolai Artemiev",
    "email": "nartemiev@google.com",
    "time": "Mon Nov 22 13:18:49 2021 +1100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Dec 30 01:16:46 2022 +0100"
  },
  "message": "spi25_statusreg: inline spi_write_register_flag()\n\nCreating the entire SPI command that should be sent to the chip in\nspi_write_register() is simpler than splitting it across two functions\nthat have to pass multiple parameters between them.\n\nAdditionally, having separate spi_write_register_flag() function\nprovided little benefit, as it was only ever called from\nspi_write_register().\n\nTested: flashrom -{r,w,E}\nTested: Tested with a W25Q128.W flash on a kasumi (AMD) dut.\n     Read SR1/SR2 with --wp-status and activated various WP ranges\n     that toggled bits in both SR1 and SR2.\n\nChange-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70974\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "31d6c76986ae239dfd2b02ed0f654a5505a0d34e",
      "old_mode": 33188,
      "old_path": "spi25_statusreg.c",
      "new_id": "249ab9a3e9df39a894cc0a93a6c054461d67293c",
      "new_mode": 33188,
      "new_path": "spi25_statusreg.c"
    }
  ]
}