)]}'
{
  "commit": "a08847581ff039e901644922c65efd07dba62cc1",
  "tree": "65fca18733796e382116eae9d3945a8c0a01cdf5",
  "parents": [
    "5eb7a58c1bc34f64c43f98578ce5b9be21a3f152"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sun Aug 25 12:29:44 2024 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sun Nov 10 13:58:05 2024 +0000"
  },
  "message": "chipset_enable: Factor PCH100 hidden-spidev workaround out\n\nIntel mandates that the SPI PCI device,  usually 00:1f.5, is hidden\non all 22nm PCHs. This applies to the whole 100 and 200 series PCHs\nas well as some special 300 and 400 series PCHs, and the respective\nserver PCHs and small-core SoCs.\n\nTo cope with the hidden PCI device, we match the LPC PCI device and\nthen crudely assume that the SPI device exists too (only its vendor\nand device IDs are hidden). We don\u0027t need this workaround for newer\ngenerations where the PCI device isn\u0027t hidden anymore,  hence split\nit out.\n\nTested read on Alder Lake P, read/erase/write on CM246 (Cannon Point).\n\nChange-Id: I77b5240b99015ecf56773f4a34436cfd3c83bdf6\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/249\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5883747835e03c61c20f121b61487f7e2d7fde0d",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "5952b561ab8a21de65e5962896bacd810aca14f7",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}