)]}'
{
  "commit": "9fe1fb71c7e53e4f44d633fe52dc33453b36848b",
  "tree": "726c76de3e2b36ea50bb50ff9e87f75aeecd3d21",
  "parents": [
    "7b629bcde47e18d094e496fb8ae537272ead0998"
  ],
  "author": {
    "name": "Ricardo Ribalda Delgado",
    "email": "ricardo.ribalda@gmail.com",
    "time": "Thu Mar 23 15:11:22 2017 +0100"
  },
  "committer": {
    "name": "David Hendricks",
    "email": "david.hendricks@gmail.com",
    "time": "Sun Sep 17 18:05:16 2017 +0000"
  },
  "message": "nicintel_eeprom: Support for I210 emulated EEprom\n\nOn the I210 family there is no MAC EEprom, instead there is a big flash\n(typically around 16Mb) with contents of the old MAC plus other stuff.\nThere is an interface to program the whole flash, but once it is\nprogrammed it enters a \"Secure Mode\" that disables the interface.\n\nLuckily, the section with the MAC can still be updated via the EEprom\ninterface. This patch adds support for this interface.\n\nroot@qt5022-fglrx:~# ./flashrom -p nicintel_eeprom:pci\u003d01:0.0 -w kk.raw -V\nflashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)\nflashrom is free software, get the source code at https://flashrom.org\n\nflashrom was built with libpci 3.4.1, GCC 5.3.0, little endian\nCommand line (5 args): ./flashrom -p nicintel_eeprom:pci\u003d01:0.0 -w kk.raw -V\nCalibrating delay loop... OS timer resolution is 1 usecs, 1856M loops per second, 10 myus \u003d 10 us,\n100 myus \u003d 102 us, 1000 myus \u003d 1017 us, 10000 myus \u003d 10044 us, 4 myus \u003d 4 us, OK.\nInitializing nicintel_eeprom programmer\nFound \"Intel I210 Gigabit Network Connection\" (8086:1533, BDF 01:00.0).\nRequested BAR is of type MEM, 32bit, not prefetchable\nRequested BAR is of type MEM, 32bit, not prefetchable\nThe following protocols are supported: Programmer-specific.\nProbing for Programmer Opaque flash chip, 0 kB: Found Programmer flash chip \"Opaque flash chip\"\n(4 kB, Programmer-specific) on nicintel_eeprom.\nFound Programmer flash chip \"Opaque flash chip\" (4 kB, Programmer-specific).\nReading old flash chip contents... done.\nErasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W\nErase/write done.\nVerifying flash... VERIFIED.\n\nChange-Id: I553f33e5dcb4412d682fc93095b29bcfed11713c\nSigned-off-by: Ricardo Ribalda Delgado \u003cricardo.ribalda@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/21431\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b5d4202b01e04b46b6005b34fac29287d5ab4e48",
      "old_mode": 33188,
      "old_path": "nicintel_eeprom.c",
      "new_id": "e2fb58480ed1fac750a5667c4dbb1c5394d8972b",
      "new_mode": 33188,
      "new_path": "nicintel_eeprom.c"
    }
  ]
}