spi25_statusreg,flashchips: add SR2 read/write support
This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.
Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.
Tested: flashrom -{r,w,E}
Tested: flashrom --wp-{enable,disable,range,list,status} at end of patch series
Tested: logged SR2 read/write values during wp commands
Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70965
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 0d7bc25..31d6c76 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -101,6 +101,33 @@
write_cmd[1] = value;
write_cmd_len = JEDEC_WRSR_OUTSIZE;
break;
+ case STATUS2:
+ if (feature_bits & FEATURE_WRSR2) {
+ write_cmd[0] = JEDEC_WRSR2;
+ write_cmd[1] = value;
+ write_cmd_len = JEDEC_WRSR2_OUTSIZE;
+ break;
+ }
+ if (feature_bits & FEATURE_WRSR_EXT) {
+ /*
+ * Writing SR2 with an extended WRSR command requires
+ * writing SR1 along with SR2, so just read SR1 and
+ * write it back
+ */
+ uint8_t sr1;
+
+ if (spi_read_register(flash, STATUS1, &sr1)) {
+ msg_cerr("Writing SR2 failed: failed to read SR1 for writeback.\n");
+ return 1;
+ }
+ write_cmd[0] = JEDEC_WRSR;
+ write_cmd[1] = sr1;
+ write_cmd[2] = value;
+ write_cmd_len = JEDEC_WRSR_EXT_OUTSIZE;
+ break;
+ }
+ msg_cerr("Cannot write SR2: unsupported by chip\n");
+ return 1;
default:
msg_cerr("Cannot write register: unknown register\n");
return 1;
@@ -122,12 +149,20 @@
int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t *value)
{
+ int feature_bits = flash->chip->feature_bits;
uint8_t read_cmd;
switch (reg) {
case STATUS1:
read_cmd = JEDEC_RDSR;
break;
+ case STATUS2:
+ if (feature_bits & (FEATURE_WRSR_EXT | FEATURE_WRSR2)) {
+ read_cmd = JEDEC_RDSR2;
+ break;
+ }
+ msg_cerr("Cannot read SR2: unsupported by chip\n");
+ return 1;
default:
msg_cerr("Cannot read register: unknown register\n");
return 1;