tree 6dca72560774a44fcc76fc8d73f5171996c7d382
parent eebeb53d65683018eb33cf3710d0cb070c12ef4f
author Jonathan Kollasch <jakllsch@kollasch.net> 1312634721 +0000
committer Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> 1312634721 +0000

Clear byte 0x92 of the LPC bridge for all CK804 (and MCP51) chipsets

The OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear
byte 0x92 in the LPC bridge configuration space.  Do the same for
all CK804 chips, assuming this to be some sort of chipset-generic
write-enable.

Currently the same chipset enable is used for MCP51 (nForce 430).
There have been reports of successful writes with its variations
(e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to
the new "unsupported chipset"-message we will get success reports in
the case this patch does not break anything on the MCP51-based boards.

See also:
http://www.flashrom.org/pipermail/flashrom/2011-July/007252.html
http://patchwork.coreboot.org/patch/3176/

Corresponding to flashrom svn r1405.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>