)]}'
{
  "commit": "9ce498ebdc7a81c29ca3041478f16dcdc0835239",
  "tree": "6dca72560774a44fcc76fc8d73f5171996c7d382",
  "parents": [
    "eebeb53d65683018eb33cf3710d0cb070c12ef4f"
  ],
  "author": {
    "name": "Jonathan Kollasch",
    "email": "jakllsch@kollasch.net",
    "time": "Sat Aug 06 12:45:21 2011 +0000"
  },
  "committer": {
    "name": "Stefan Tauner",
    "email": "stefan.tauner@alumni.tuwien.ac.at",
    "time": "Sat Aug 06 12:45:21 2011 +0000"
  },
  "message": "Clear byte 0x92 of the LPC bridge for all CK804 (and MCP51) chipsets\n\nThe OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear\nbyte 0x92 in the LPC bridge configuration space.  Do the same for\nall CK804 chips, assuming this to be some sort of chipset-generic\nwrite-enable.\n\nCurrently the same chipset enable is used for MCP51 (nForce 430).\nThere have been reports of successful writes with its variations\n(e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to\nthe new \"unsupported chipset\"-message we will get success reports in\nthe case this patch does not break anything on the MCP51-based boards.\n\nSee also:\nhttp://www.flashrom.org/pipermail/flashrom/2011-July/007252.html\nhttp://patchwork.coreboot.org/patch/3176/\n\nCorresponding to flashrom svn r1405.\n\nSigned-off-by: Jonathan Kollasch \u003cjakllsch@kollasch.net\u003e\nAcked-by: Joshua Roys \u003croysjosh@gmail.com\u003e\nAcked-by: Stefan Tauner \u003cstefan.tauner@alumni.tuwien.ac.at\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c6015f0cfb357eb0b828164c179337919a165c7b",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "97001a7e8dfd638b24d4497818c529e7360efc12",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}