diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index 7b973de..2ab5c75 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -718,6 +718,21 @@
 SR1, 0x22 to SR2 and 0x33 to SR3. Shorter value is padded to 24 bits with
 zeroes on the left. See datasheet for chosen chip for details about the
 registers content.
+.sp
+.TP
+.B Write protection
+.sp
+Chips with emulated WP: W25Q128FV.
+.sp
+You can simulate state of hardware protection pin (WP) with the
+.sp
+.B "  flashrom -p dummy:hwwp=state"
+.sp
+syntax where
+.B state
+is "yes" or "no" (default value). "yes" means active state of the pin implies
+that chip is write-protected (on real hardware the pin is usually negated, but
+not here).
 .SS
 .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\
 , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\