)]}'
{
  "commit": "9ad4255b5e206899351b446dec96b84c989627b6",
  "tree": "1f7069b9085f188b261d7c93ceca03b48f32d439",
  "parents": [
    "2822888c810eaf2d68271f4dac4a0ad639221fd3"
  ],
  "author": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Wed Sep 15 10:20:16 2010 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Wed Sep 15 10:20:16 2010 +0000"
  },
  "message": "Delay between probe and subsequent operations\n\nSome flash chips need time to exit ID mode, and while we take care of\ncorrect timing for the matching probe, subsequent probes may have\ntotally different timing, and that can lead to garbage responses from\nthe flash chip during the first accesses after the probe sequence is\ndone.\nDelay 100 ms between the last probe and any subsequent operation.\nTo ensure maximum correctness, we would have to reset the chip first in\ncase the last probe function left the chip in an undefined (non-read)\nstate. That will be possible once struct flashchip has a .reset\nfunction.\n\nThis fixes unstable erase/read/write for some flahs chips on nic3com and\npossible other use cases as well.\n\nThanks to Maciej Pijanka for reporting the issue and testing patches.\n\nCorresponding to flashrom svn r1172.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nAcked-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d78c5755c1ccd4163ce3bb5e1b3ad7912579072e",
      "old_mode": 33188,
      "old_path": "cli_classic.c",
      "new_id": "09504d7fb277b85b4b6594f746573d97f74b0ab9",
      "new_mode": 33188,
      "new_path": "cli_classic.c"
    }
  ]
}