Add support for Realtek RTL8169
And some cleanups including the removal of any left traces of the
nicsmc1211 programmer. The RTL8169 still needs someone to test it,
but it's good enough to be in the tree now.
Corresponding to flashrom svn r1586.
Signed-off-by: Sergey Lichack <shadowpilot34@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Mathias Krause <mathias.krause@secunet.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
diff --git a/flashrom.8 b/flashrom.8
index 33e6e23..bf671c2 100644
--- a/flashrom.8
+++ b/flashrom.8
@@ -172,9 +172,7 @@
.sp
.BR "* nic3com" " (for flash ROMs on 3COM network cards)"
.sp
-.BR "* nicrealtek" " (for flash ROMs on Realtek network cards)"
-.sp
-.BR "* nicsmc1211" " (for flash ROMs on RTL8139-compatible SMC2 network cards)"
+.BR "* nicrealtek" " (for flash ROMs on Realtek and SMC 1211 network cards)"
.sp
.BR "* nicnatsemi" " (for flash ROMs on National Semiconductor DP838* network \
cards)"
@@ -532,7 +530,7 @@
.B content
is an 8-bit hexadecimal value.
.SS
-.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\
+.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel\
" , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\
" , " satamv" ", and " atahpt " programmers
These programmers have an option to specify the PCI address of the card
@@ -761,7 +759,7 @@
needs raw memory access, PCI configuration space access, raw I/O port
access (x86) and MSR access (x86).
.sp
-.BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi "
+.BR nic3com ", " nicrealtek " and " nicnatsemi "
need PCI configuration space read access and raw I/O port access.
.sp
.B atahpt
@@ -792,7 +790,7 @@
.B dummy
needs no access permissions at all.
.sp
-.BR internal ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " nicnatsemi ", "
+.BR internal ", " nic3com ", " nicrealtek ", " nicnatsemi ", "
.BR gfxnvidia ", " drkaiser ", " satasii ", " satamv " and " atahpt
have to be run as superuser/root, and need additional raw access permission.
.sp
diff --git a/flashrom.c b/flashrom.c
index f6185d0..fdc5412 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -95,7 +95,6 @@
{
/* This programmer works for Realtek RTL8139 and SMC 1211. */
.name = "nicrealtek",
- //.name = "nicsmc1211",
.init = nicrealtek_init,
.map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap,
diff --git a/nicrealtek.c b/nicrealtek.c
index 08ff219..779d023 100644
--- a/nicrealtek.c
+++ b/nicrealtek.c
@@ -28,20 +28,18 @@
#define PCI_VENDOR_ID_REALTEK 0x10ec
#define PCI_VENDOR_ID_SMC1211 0x1113
-#define BIOS_ROM_ADDR 0xD4
-#define BIOS_ROM_DATA 0xD7
+static int bios_rom_addr, bios_rom_data;
const struct pcidev_status nics_realtek[] = {
{0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
- {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */
+ {0x10ec, 0x8169, NT, "Realtek", "RTL8169"},
+ {0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */
{0},
};
-static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr);
-static uint8_t nicrealtek_chip_readb(const struct flashctx *flash,
- const chipaddr addr);
+static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
+static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr);
static const struct par_programmer par_programmer_nicrealtek = {
.chip_readb = nicrealtek_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -62,6 +60,20 @@
int nicrealtek_init(void)
{
+ /* Beware, this ignores the vendor ID! */
+ switch (pcidev_dev->device_id) {
+ case 0x8139: /* RTL8139 */
+ case 0x1211: /* SMC 1211TX */
+ default:
+ bios_rom_addr = 0xD4;
+ bios_rom_data = 0xD7;
+ break;
+ case 0x8169: /* RTL8169 */
+ bios_rom_addr = 0x30;
+ bios_rom_data = 0x33;
+ break;
+ }
+
if (rget_io_perms())
return 1;
@@ -75,42 +87,40 @@
return 0;
}
-static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr)
+static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
{
/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
- io_base_addr + BIOS_ROM_ADDR);
+ io_base_addr + bios_rom_addr);
/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
- io_base_addr + BIOS_ROM_ADDR);
+ io_base_addr + bios_rom_addr);
}
-static uint8_t nicrealtek_chip_readb(const struct flashctx *flash,
- const chipaddr addr)
+static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
{
uint8_t val;
/* FIXME: Can we skip reading the old data and simply use 0? */
/* Read old data. */
- val = INB(io_base_addr + BIOS_ROM_DATA);
+ val = INB(io_base_addr + bios_rom_data);
/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
- io_base_addr + BIOS_ROM_ADDR);
+ io_base_addr + bios_rom_addr);
/* Read new data. */
- val = INB(io_base_addr + BIOS_ROM_DATA);
+ val = INB(io_base_addr + bios_rom_data);
/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
- io_base_addr + BIOS_ROM_ADDR);
+ io_base_addr + bios_rom_addr);
return val;
}