)]}'
{
  "commit": "98bdcb46de824e6671671ed83465cec3087f69ba",
  "tree": "08c53170c94b115596d4ca58b0e839cdc9a03ff3",
  "parents": [
    "7dcb6f33d0e97154b3533917fad3dea0dad676bc"
  ],
  "author": {
    "name": "Jeremy Kerr",
    "email": "jk@codeconstruct.com.au",
    "time": "Sun May 23 17:58:06 2021 +0800"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Thu Jan 05 16:15:22 2023 +0000"
  },
  "message": "buspirate: Add psus option\n\nThis change adds a \u0027psus\u003d\u003con|off\u003e\u0027 option, to control the external Vcc\nstate of the bus pirate, allowing hardware where the SPI flash chip is\npowered by the 3V3/5V lines directly.\n\nChange-Id: I8a7d4b40c0f7f04f6976f6757f05b61f2c9958f9\nSigned-off-by: Jeremy Kerr \u003cjk@codeconstruct.com.au\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54887\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71389\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ae939e346d0652aecf59b5c37186a1e91b325677",
      "old_mode": 33188,
      "old_path": "buspirate_spi.c",
      "new_id": "39b9c5236cb96ffcc7b1e66575067ae97ee8acff",
      "new_mode": 33188,
      "new_path": "buspirate_spi.c"
    },
    {
      "type": "modify",
      "old_id": "e67cdea6ea18fa5164dcb97998b5f2a44622021c",
      "old_mode": 33188,
      "old_path": "flashrom.8.tmpl",
      "new_id": "9ec4d775b5018c3362259a69a64214d63448789f",
      "new_mode": 33188,
      "new_path": "flashrom.8.tmpl"
    }
  ]
}