diff --git a/82802ab.c b/82802ab.c
index 2580706..cd59c07 100644
--- a/82802ab.c
+++ b/82802ab.c
@@ -29,7 +29,6 @@
 #include "flash.h"
 #include "chipdrivers.h"
 
-// I need that Berkeley bit-map printer
 void print_status_82802ab(uint8_t status)
 {
 	msg_cdbg("%s", status & 0x80 ? "Ready:" : "Busy:");
@@ -44,8 +43,7 @@
 int probe_82802ab(struct flashchip *flash)
 {
 	chipaddr bios = flash->virtual_memory;
-	uint8_t id1, id2;
-	uint8_t flashcontent1, flashcontent2;
+	uint8_t id1, id2, flashcontent1, flashcontent2;
 	int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) != 0;
 
 	/* Reset to get a clean state */
@@ -69,7 +67,10 @@
 	if (!oddparity(id1))
 		msg_cdbg(", id1 parity violation");
 
-	/* Read the product ID location again. We should now see normal flash contents. */
+	/*
+	 * Read the product ID location again. We should now see normal
+	 * flash contents.
+	 */
 	flashcontent1 = chip_readb(bios + (0x00 << shifted));
 	flashcontent2 = chip_readb(bios + (0x01 << shifted));
 
@@ -112,14 +113,13 @@
 	//chipaddr wrprotect = flash->virtual_registers + page + 2;
 
 	for (i = 0; i < flash->total_size * 1024; i+= flash->page_size)
-	{
 		chip_writeb(0, flash->virtual_registers + i + 2);
-	}
 
 	return 0;
 }
 
-int erase_block_82802ab(struct flashchip *flash, unsigned int page, unsigned int pagesize)
+int erase_block_82802ab(struct flashchip *flash, unsigned int page,
+			unsigned int pagesize)
 {
 	chipaddr bios = flash->virtual_memory;
 	uint8_t status;
@@ -178,7 +178,7 @@
 		msg_cdbg("unlocked!\n");
 		can_unlock = 1;
 	}
-	
+
 	/* Read block lock-bits */
 	for (i = 0; i < flash->total_size * 1024; i+= (64 * 1024)) {
 		bcfg = chip_readb(bios + i + 2); // read block lock config
diff --git a/a25.c b/a25.c
index f38626c..c449be0 100644
--- a/a25.c
+++ b/a25.c
@@ -31,7 +31,7 @@
 	msg_cdbg("Chip status register is %02x\n", status);
 
 	msg_cdbg("Chip status register: Status Register Write Disable "
-		     "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+		 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
 	spi_prettyprint_status_register_bit(status, 6);
 	spi_prettyprint_status_register_bit(status, 5);
 	spi_prettyprint_status_register_bit(status, 4);
@@ -48,7 +48,7 @@
 	msg_cdbg("Chip status register is %02x\n", status);
 
 	msg_cdbg("Chip status register: Status Register Write Disable "
-		     "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+		 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
 	spi_prettyprint_status_register_bit(status, 6);
 	spi_prettyprint_status_register_bit(status, 5);
 	spi_prettyprint_status_register_bp3210(status, 2);
@@ -64,7 +64,7 @@
 	msg_cdbg("Chip status register is %02x\n", status);
 
 	msg_cdbg("Chip status register: Status Register Write Disable "
-		     "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+		 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
 	msg_cdbg("Chip status register: Sector Protect Size (SEC) "
 		 "is %i KB\n", (status & (1 << 6)) ? 4 : 64);
 	msg_cdbg("Chip status register: Top/Bottom (TB) "
@@ -83,7 +83,7 @@
 	msg_cdbg("Chip status register is %02x\n", status);
 
 	msg_cdbg("Chip status register: Status Register Write Disable "
-		     "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+		 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
 	msg_cdbg("Chip status register: Sector Protect Size (SEC) "
 		 "is %i KB\n", (status & (1 << 6)) ? 4 : 64);
 	msg_cdbg("Chip status register: Top/Bottom (TB) "
diff --git a/bitbang_spi.c b/bitbang_spi.c
index 3c718af..4219a62 100644
--- a/bitbang_spi.c
+++ b/bitbang_spi.c
@@ -68,13 +68,13 @@
 		const unsigned char *writearr, unsigned char *readarr);
 
 static const struct spi_programmer spi_programmer_bitbang = {
-	.type = SPI_CONTROLLER_BITBANG,
-	.max_data_read = MAX_DATA_READ_UNLIMITED,
-	.max_data_write = MAX_DATA_WRITE_UNLIMITED,
-	.command = bitbang_spi_send_command,
-	.multicommand = default_spi_send_multicommand,
-	.read = default_spi_read,
-	.write_256 = default_spi_write_256,
+	.type		= SPI_CONTROLLER_BITBANG,
+	.max_data_read	= MAX_DATA_READ_UNLIMITED,
+	.max_data_write	= MAX_DATA_WRITE_UNLIMITED,
+	.command	= bitbang_spi_send_command,
+	.multicommand	= default_spi_send_multicommand,
+	.read		= default_spi_read,
+	.write_256	= default_spi_write_256,
 };
 
 int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod)
diff --git a/board_enable.c b/board_enable.c
index 107ca0c..3f4c66a 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -179,7 +179,7 @@
 static const struct winbond_port w83627hf[3] = {
 	UNIMPLEMENTED_PORT,
 	{w83627hf_port2_mux, 0x08, 0, 0xF0},
-	UNIMPLEMENTED_PORT
+	UNIMPLEMENTED_PORT,
 };
 
 static const struct winbond_mux w83627ehf_port2_mux[8] = {
@@ -190,7 +190,7 @@
 	{0x2A, 0x01, 0x01},	/* or keyboard/mouse interface */
 	{0x2A, 0x01, 0x01},
 	{0x2A, 0x01, 0x01},
-	{0x2A, 0x01, 0x01}
+	{0x2A, 0x01, 0x01},
 };
 
 static const struct winbond_port w83627ehf[6] = {
@@ -199,7 +199,7 @@
 	UNIMPLEMENTED_PORT,
 	UNIMPLEMENTED_PORT,
 	UNIMPLEMENTED_PORT,
-	UNIMPLEMENTED_PORT
+	UNIMPLEMENTED_PORT,
 };
 
 static const struct winbond_mux w83627thf_port4_mux[8] = {
@@ -210,7 +210,7 @@
 	{0x2D, 0x10, 0x10},	/* or PWROK */
 	{0x2D, 0x20, 0x20},	/* or suspend LED */
 	{0x2D, 0x40, 0x40},	/* or panel switch input */
-	{0x2D, 0x80, 0x80}	/* or panel switch output */
+	{0x2D, 0x80, 0x80},	/* or panel switch output */
 };
 
 static const struct winbond_port w83627thf[5] = {
@@ -218,7 +218,7 @@
 	UNIMPLEMENTED_PORT,	/* GPIO2 */
 	UNIMPLEMENTED_PORT,	/* GPIO3 */
 	{w83627thf_port4_mux, 0x09, 1, 0xF4},
-	UNIMPLEMENTED_PORT	/* GPIO5 */
+	UNIMPLEMENTED_PORT,	/* GPIO5 */
 };
 
 static const struct winbond_chip winbond_chips[] = {
@@ -561,7 +561,8 @@
 
 	id = sio_read(0x2E, 0x20);
 	if (id != chipid) {
-		msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid);
+		msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
+			 id, chipid);
 		return -1;
 	}
 
@@ -811,13 +812,13 @@
 {
 	struct pci_dev *dev;
 
-	dev = pci_dev_find(0x10DE, 0x0050);	/* NVIDIA CK804 ISA Bridge. */
+	dev = pci_dev_find(0x10DE, 0x0050);	/* NVIDIA CK804 ISA bridge. */
 	if (!dev) {
 		msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
 		return -1;
 	}
 
-	/* one of those bits seems to be connected to TBL#, but -ENOINFO. */
+	/* One of those bits seems to be connected to TBL#, but -ENOINFO. */
 	pci_write_byte(dev, 0x92, 0);
 
 	return 0;
@@ -851,8 +852,7 @@
 static int nvidia_mcp_gpio_set(int gpio, int raise)
 {
 	struct pci_dev *dev;
-	uint16_t base;
-	uint16_t devclass;
+	uint16_t base, devclass;
 	uint8_t tmp;
 
 	if ((gpio < 0) || (gpio >= 0x40)) {
@@ -860,7 +860,7 @@
 		return -1;
 	}
 
-	/* First, check the ISA Bridge */
+	/* First, check the ISA bridge */
 	dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
 	switch (dev->device_id) {
 	case 0x0030: /* CK804 */
@@ -1092,7 +1092,7 @@
 
 /*
  * Suited for:
- *  - Asus A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
+ *  - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
  * Datasheet(s) used:
  *  - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
  */
@@ -1101,7 +1101,7 @@
 	struct pci_dev *dev;
 	uint32_t reg;
 
-	dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus Controller */
+	dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
 	if (!dev) {
 		msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
 		return -1;
@@ -1128,43 +1128,43 @@
 	struct pci_dev *dev;
 	uint32_t tmp, base;
 
-	static const uint32_t nonmuxed_gpos  = 0x58000101; /* GPPO {0,8,27,28,30} are always available */
+	/* GPPO {0,8,27,28,30} are always available */
+	static const uint32_t nonmuxed_gpos  = 0x58000101;
 
 	static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
-	  {0},
-	  {0xB0, 0x0001, 0x0000},        /* GPO1... */
-	  {0xB0, 0x0001, 0x0000},
-	  {0xB0, 0x0001, 0x0000},
-	  {0xB0, 0x0001, 0x0000},
-	  {0xB0, 0x0001, 0x0000},
-	  {0xB0, 0x0001, 0x0000},
-	  {0xB0, 0x0001, 0x0000},        /* ...GPO7: GENCFG bit 0 */
-	  {0},
-	  {0xB0, 0x0100, 0x0000},        /* GPO9:  GENCFG bit 8 */
-	  {0xB0, 0x0200, 0x0000},        /* GPO10: GENCFG bit 9 */
-	  {0xB0, 0x0400, 0x0000},        /* GPO11: GENCFG bit 10 */
-	  {0x4E, 0x0100, 0x0000},        /* GPO12... */
-	  {0x4E, 0x0100, 0x0000},
-	  {0x4E, 0x0100, 0x0000},        /* ...GPO14: XBCS bit 8 */
-	  {0xB2, 0x0002, 0x0002},        /* GPO15... */
-	  {0xB2, 0x0002, 0x0002},        /* ...GPO16: GENCFG bit 17 */
-	  {0xB2, 0x0004, 0x0004},        /* GPO17: GENCFG bit 18 */
-	  {0xB2, 0x0008, 0x0008},        /* GPO18: GENCFG bit 19 */
-	  {0xB2, 0x0010, 0x0010},        /* GPO19: GENCFG bit 20 */
-	  {0xB2, 0x0020, 0x0020},        /* GPO20: GENCFG bit 21 */
-	  {0xB2, 0x0040, 0x0040},        /* GPO21: GENCFG bit 22 */
-	  {0xB2, 0x1000, 0x1000},        /* GPO22... */
-	  {0xB2, 0x1000, 0x1000},        /* ...GPO23: GENCFG bit 28 */
-	  {0xB2, 0x2000, 0x2000},        /* GPO24: GENCFG bit 29 */
-	  {0xB2, 0x4000, 0x4000},        /* GPO25: GENCFG bit 30 */
-	  {0xB2, 0x8000, 0x8000},        /* GPO26: GENCFG bit 31 */
-	  {0},
-	  {0},
-	  {0x4E, 0x0100, 0x0000},        /* ...GPO29: XBCS bit 8 */
-	  {0}
+		{0},
+		{0xB0, 0x0001, 0x0000},        /* GPO1... */
+		{0xB0, 0x0001, 0x0000},
+		{0xB0, 0x0001, 0x0000},
+		{0xB0, 0x0001, 0x0000},
+		{0xB0, 0x0001, 0x0000},
+		{0xB0, 0x0001, 0x0000},
+		{0xB0, 0x0001, 0x0000},        /* ...GPO7: GENCFG bit 0 */
+		{0},
+		{0xB0, 0x0100, 0x0000},        /* GPO9:  GENCFG bit 8 */
+		{0xB0, 0x0200, 0x0000},        /* GPO10: GENCFG bit 9 */
+		{0xB0, 0x0400, 0x0000},        /* GPO11: GENCFG bit 10 */
+		{0x4E, 0x0100, 0x0000},        /* GPO12... */
+		{0x4E, 0x0100, 0x0000},
+		{0x4E, 0x0100, 0x0000},        /* ...GPO14: XBCS bit 8 */
+		{0xB2, 0x0002, 0x0002},        /* GPO15... */
+		{0xB2, 0x0002, 0x0002},        /* ...GPO16: GENCFG bit 17 */
+		{0xB2, 0x0004, 0x0004},        /* GPO17: GENCFG bit 18 */
+		{0xB2, 0x0008, 0x0008},        /* GPO18: GENCFG bit 19 */
+		{0xB2, 0x0010, 0x0010},        /* GPO19: GENCFG bit 20 */
+		{0xB2, 0x0020, 0x0020},        /* GPO20: GENCFG bit 21 */
+		{0xB2, 0x0040, 0x0040},        /* GPO21: GENCFG bit 22 */
+		{0xB2, 0x1000, 0x1000},        /* GPO22... */
+		{0xB2, 0x1000, 0x1000},        /* ...GPO23: GENCFG bit 28 */
+		{0xB2, 0x2000, 0x2000},        /* GPO24: GENCFG bit 29 */
+		{0xB2, 0x4000, 0x4000},        /* GPO25: GENCFG bit 30 */
+		{0xB2, 0x8000, 0x8000},        /* GPO26: GENCFG bit 31 */
+		{0},
+		{0},
+		{0x4E, 0x0100, 0x0000},        /* ...GPO29: XBCS bit 8 */
+		{0}
 	};
 
-
 	dev = pci_dev_find(0x8086, 0x7110);	/* Intel PIIX4 ISA bridge */
 	if (!dev) {
 		msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
@@ -1177,10 +1177,12 @@
 		return -1;
 	}
 
-	if ( (((1 << gpo) & nonmuxed_gpos) == 0) &&
-	     (pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value ) {
-	  msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
-	  return -1;
+	if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
+	     (pci_read_word(dev, piix4_gpo[gpo].reg)
+	     & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value) {
+		msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n",
+			 gpo);
+		return -1;
 	}
 
 	dev = pci_dev_find(0x8086, 0x7113);	/* Intel PIIX4 PM */
@@ -1315,7 +1317,7 @@
 		/* libpci before version 2.2.4 does not store class info. */
 		device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
 		if ((dev->vendor_id == 0x8086) &&
-		    (device_class == 0x0601)) { /* ISA Bridge */
+		    (device_class == 0x0601)) { /* ISA bridge */
 			/* Is this device in our list? */
 			for (i = 0; intel_ich_gpio_table[i].id; i++)
 				if (dev->device_id == intel_ich_gpio_table[i].id)
@@ -1327,7 +1329,7 @@
 	}
 
 	if (!dev) {
-		msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
+		msg_perr("\nERROR: No known Intel LPC bridge found.\n");
 		return -1;
 	}
 
@@ -1347,13 +1349,13 @@
 		allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
 
 	if (!allowed) {
-		msg_perr("\nERROR: This Intel LPC Bridge does not allow"
-			" setting GPIO%02d\n", gpio);
+		msg_perr("\nERROR: This Intel LPC bridge does not allow"
+			 " setting GPIO%02d\n", gpio);
 		return -1;
 	}
 
-	msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
-	       raise ? "Rais" : "Dropp", gpio);
+	msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
+		 raise ? "Rais" : "Dropp", gpio);
 
 	if (gpio < 32) {
 		/* Set line to GPIO. */
@@ -1371,7 +1373,7 @@
 		if (dev->device_id > 0x2800) {
 			tmp = INL(base);
 			if (!(tmp & (1 << gpio))) {
-				msg_perr("\nERROR: This Intel LPC Bridge"
+				msg_perr("\nERROR: This Intel LPC bridge"
 					" does not allow setting GPIO%02d\n",
 					gpio);
 				return -1;
@@ -1403,7 +1405,7 @@
 		if (dev->device_id > 0x2800) {
 			tmp = INL(base + 30);
 			if (!(tmp & (1 << gpio))) {
-				msg_perr("\nERROR: This Intel LPC Bridge"
+				msg_perr("\nERROR: This Intel LPC bridge"
 					" does not allow setting GPIO%02d\n",
 					gpio + 32);
 				return -1;
@@ -1432,7 +1434,7 @@
 
 		tmp = INL(base + 40);
 		if (!(tmp & (1 << gpio))) {
-			msg_perr("\nERROR: This Intel LPC Bridge does "
+			msg_perr("\nERROR: This Intel LPC bridge does "
 				"not allow setting GPIO%02d\n", gpio + 64);
 			return -1;
 		}
@@ -1607,10 +1609,10 @@
 {
 	int ret;
 
-	/* vendor BIOS ends up in LDN6... maybe the board enable is wrong,
+	/* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
 	 * or perhaps it's not needed at all?
-	 * the regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
-	 * were in the right LDN, it would have to be GPIO1 or GPIO3
+	 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
+	 * were in the right LDN, it would have to be GPIO1 or GPIO3.
 	 */
 /*
 	ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
@@ -1659,10 +1661,9 @@
 static int via_apollo_gpo_set(int gpio, int raise)
 {
 	struct pci_dev *dev;
-	uint32_t base;
-	uint32_t tmp;
+	uint32_t base, tmp;
 
-	/* VT82C686 Power management */
+	/* VT82C686 power management */
 	dev = pci_dev_find(0x1106, 0x3057);
 	if (!dev) {
 		msg_perr("\nERROR: VT82C686 PM device not found.\n");
@@ -1670,24 +1671,23 @@
 	}
 
 	msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
-	       raise ? "Rais" : "Dropp", gpio);
+		 raise ? "Rais" : "Dropp", gpio);
 
-	/* select GPO function on multiplexed pins */
+	/* Select GPO function on multiplexed pins. */
 	tmp = pci_read_byte(dev, 0x54);
-	switch(gpio)
-	{
-		case 0:
-			tmp &= ~0x03;
-			break;
-		case 1:
-			tmp |= 0x04;
-			break;
-		case 2:
-			tmp |= 0x08;
-			break;
-		case 3:
-			tmp |= 0x10;
-			break;
+	switch (gpio) {
+	case 0:
+		tmp &= ~0x03;
+		break;
+	case 1:
+		tmp |= 0x04;
+		break;
+	case 2:
+		tmp |= 0x08;
+		break;
+	case 3:
+		tmp |= 0x10;
+		break;
 	}
 	pci_write_byte(dev, 0x54, tmp);
 
@@ -1880,8 +1880,8 @@
 	/* Check line */
 	if ((port > 4) || /* also catches unsigned -1 */
 	    ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
-	    msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line);
-	    return -1;
+		msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line);
+		return -1;
 	}
 
 	/* Find the IT8712F. */
@@ -1906,7 +1906,7 @@
 		return -1;
 	}
 
-	/* set GPIO. */
+	/* Set GPIO. */
 	tmp = INB(base + port);
 	if (raise)
 	    tmp |= 1 << line;
@@ -2091,8 +2091,8 @@
  * Match boards on coreboot table gathered vendor and part name.
  * Require main PCI IDs to match too as extra safety.
  */
-static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
-							    const char *part)
+static const struct board_pciid_enable *board_match_coreboot_name(
+					const char *vendor, const char *part)
 {
 	const struct board_pciid_enable *board = board_pciid_enables;
 	const struct board_pciid_enable *partmatch = NULL;
@@ -2119,7 +2119,7 @@
 			/* a second entry has a matching part name */
 			msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
 			msg_pinfo("At least vendors '%s' and '%s' match.\n",
-			       partmatch->lb_vendor, board->lb_vendor);
+				  partmatch->lb_vendor, board->lb_vendor);
 			msg_perr("Please use the full -m vendor:part syntax.\n");
 			return NULL;
 		}
@@ -2135,7 +2135,7 @@
 		 * expected to fix flashrom, too.
 		 */
 		msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
-		       vendor, part);
+			 vendor, part);
 	}
 	return NULL;
 }
@@ -2144,7 +2144,8 @@
  * Match boards on PCI IDs and subsystem IDs.
  * Second set of IDs can be main only or missing completely.
  */
-const static struct board_pciid_enable *board_match_pci_card_ids(enum board_match_phase phase)
+const static struct board_pciid_enable *board_match_pci_card_ids(
+						enum board_match_phase phase)
 {
 	const struct board_pciid_enable *board = board_pciid_enables;
 
@@ -2177,8 +2178,8 @@
 		if (board->dmi_pattern) {
 			if (!has_dmi_support) {
 				msg_perr("WARNING: Can't autodetect %s %s,"
-				       " DMI info unavailable.\n",
-				       board->vendor_name, board->board_name);
+					 " DMI info unavailable.\n",
+					 board->vendor_name, board->board_name);
 				continue;
 			} else {
 				if (!dmi_match(board->dmi_pattern))
@@ -2202,12 +2203,12 @@
 
 	if (!force_boardenable) {
 		msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
-		       "code has not been tested, and thus will not be executed by default.\n"
-		       "Depending on your hardware environment, erasing, writing or even probing\n"
-		       "can fail without running the board specific code.\n\n"
-		       "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
-		       "\"internal programmer\") for details.\n",
-		       board->vendor_name, board->board_name);
+			  "code has not been tested, and thus will not be executed by default.\n"
+			  "Depending on your hardware environment, erasing, writing or even probing\n"
+			  "can fail without running the board specific code.\n\n"
+			  "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
+			  "\"internal programmer\") for details.\n",
+			  board->vendor_name, board->board_name);
 		return 1;
 	}
 	msg_pinfo("NOTE: Running an untested board enable procedure.\n"
diff --git a/buspirate_spi.c b/buspirate_spi.c
index f872309..467d271 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -50,7 +50,8 @@
 #define sp_flush_incoming(...) 0
 #endif
 
-static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt)
+static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt,
+			      unsigned int readcnt)
 {
 	int i, ret = 0;
 
@@ -90,13 +91,13 @@
 		const unsigned char *writearr, unsigned char *readarr);
 
 static const struct spi_programmer spi_programmer_buspirate = {
-	.type = SPI_CONTROLLER_BUSPIRATE,
-	.max_data_read = 12,
-	.max_data_write = 12,
-	.command = buspirate_spi_send_command,
-	.multicommand = default_spi_send_multicommand,
-	.read = default_spi_read,
-	.write_256 = default_spi_write_256,
+	.type		= SPI_CONTROLLER_BUSPIRATE,
+	.max_data_read	= 12,
+	.max_data_write	= 12,
+	.command	= buspirate_spi_send_command,
+	.multicommand	= default_spi_send_multicommand,
+	.read		= default_spi_read,
+	.write_256	= default_spi_write_256,
 };
 
 static const struct buspirate_spispeeds spispeeds[] = {
@@ -108,7 +109,7 @@
 	{"2.6M",	0x5},
 	{"4M",		0x6},
 	{"8M",		0x7},
-	{NULL,		0x0}
+	{NULL,		0x0},
 };
 
 static int buspirate_spi_shutdown(void *data)
@@ -149,11 +150,9 @@
 int buspirate_spi_init(void)
 {
 	unsigned char buf[512];
-	int ret = 0;
-	int i;
+	int ret = 0, i, spispeed = 0x7;
 	char *dev = NULL;
 	char *speed = NULL;
-	int spispeed = 0x7;
 
 	dev = extract_programmer_param("dev");
 	if (!dev || !strlen(dev)) {
diff --git a/chipset_enable.c b/chipset_enable.c
index 0f854c8..43f7255 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -77,7 +77,8 @@
 	rpci_write_byte(dev, 0x40, new);
 	newer = pci_read_byte(dev, 0x40);
 	if (newer != new) {
-		msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
+		msg_pinfo("tried to set register 0x%x to 0x%x on %s "
+			  "failed (WARNING ONLY)\n", 0x40, new, name);
 		msg_pinfo("Stuck at 0x%x\n", newer);
 		return -1;
 	}
@@ -87,7 +88,7 @@
 static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
 {
 	struct pci_dev *sbdev;
-	
+
 	sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
 	if (!sbdev)
 		sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
@@ -97,8 +98,8 @@
 		msg_perr("No southbridge found for %s!\n", name);
 	if (sbdev)
 		msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
-			     sbdev->vendor_id, sbdev->device_id,
-			     sbdev->bus, sbdev->dev, sbdev->func);
+			 sbdev->vendor_id, sbdev->device_id,
+			 sbdev->bus, sbdev->dev, sbdev->func);
 	return sbdev;
 }
 
@@ -165,7 +166,8 @@
 	rpci_write_byte(sbdev, 0x45, new);
 	newer = pci_read_byte(sbdev, 0x45);
 	if (newer != new) {
-		msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
+		msg_pinfo("tried to set register 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY)\n", 0x45, new, name);
 		msg_pinfo("Stuck at 0x%x\n", newer);
 		ret = -1;
 	}
@@ -191,7 +193,8 @@
 	rpci_write_byte(sbdev, 0x45, new);
 	newer = pci_read_byte(sbdev, 0x45);
 	if (newer != new) {
-		msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
+		msg_pinfo("tried to set register 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY)\n", 0x45, new, name);
 		msg_pinfo("Stuck at 0x%x\n", newer);
 		ret = -1;
 	}
@@ -238,7 +241,8 @@
 	rpci_write_word(dev, xbcs, new);
 
 	if (pci_read_word(dev, xbcs) != new) {
-		msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
+		msg_pinfo("tried to set 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY)\n", xbcs, new, name);
 		return -1;
 	}
 
@@ -261,9 +265,9 @@
 	old = pci_read_byte(dev, bios_cntl);
 
 	msg_pdbg("\nBIOS Lock Enable: %sabled, ",
-		     (old & (1 << 1)) ? "en" : "dis");
+		 (old & (1 << 1)) ? "en" : "dis");
 	msg_pdbg("BIOS Write Enable: %sabled, ",
-		     (old & (1 << 0)) ? "en" : "dis");
+		 (old & (1 << 0)) ? "en" : "dis");
 	msg_pdbg("BIOS_CNTL is 0x%x\n", old);
 
 	/*
@@ -271,10 +275,10 @@
 	 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
 	 * 1 = BIOS region SMM protection is enabled.
 	 * The BIOS Region is not writable unless all processors are in SMM."
-	 * In earlier chipsets this bit is reserved. */
-	if (old & (1 << 5)) {
+	 * In earlier chipsets this bit is reserved.
+	 */
+	if (old & (1 << 5))
 		msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n");
-	}
 
 	new = old | 1;
 	if (new == old)
@@ -283,7 +287,8 @@
 	rpci_write_byte(dev, bios_cntl, new);
 
 	if (pci_read_byte(dev, bios_cntl) != new) {
-		msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
+		msg_pinfo("tried to set 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY)\n", bios_cntl, new, name);
 		return -1;
 	}
 
@@ -304,17 +309,13 @@
 static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
 {
 	uint32_t fwh_conf;
-	int i;
 	char *idsel = NULL;
-	int tmp;
-	int max_decode_fwh_idsel = 0;
-	int max_decode_fwh_decode = 0;
+	int i, tmp, max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
 	int contiguous = 1;
 
 	idsel = extract_programmer_param("fwh_idsel");
 	if (idsel && strlen(idsel)) {
-		uint64_t fwh_idsel_old;
-		uint64_t fwh_idsel;
+		uint64_t fwh_idsel_old, fwh_idsel;
 		errno = 0;
 		/* Base 16, nothing else makes sense. */
 		fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
@@ -358,9 +359,9 @@
 	for (i = 7; i >= 0; i--) {
 		tmp = (fwh_conf >> (i * 4)) & 0xf;
 		msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
-			     (0x1ff8 + i) * 0x80000,
-			     (0x1ff0 + i) * 0x80000,
-			     tmp);
+			 (0x1ff8 + i) * 0x80000,
+			 (0x1ff0 + i) * 0x80000,
+			 tmp);
 		if ((tmp == 0) && contiguous) {
 			max_decode_fwh_idsel = (8 - i) * 0x80000;
 		} else {
@@ -372,9 +373,9 @@
 	for (i = 3; i >= 0; i--) {
 		tmp = (fwh_conf >> (i * 4)) & 0xf;
 		msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
-			     (0xff4 + i) * 0x100000,
-			     (0xff0 + i) * 0x100000,
-			     tmp);
+			 (0xff4 + i) * 0x100000,
+			 (0xff0 + i) * 0x100000,
+			 tmp);
 		if ((tmp == 0) && contiguous) {
 			max_decode_fwh_idsel = (8 - i) * 0x100000;
 		} else {
@@ -387,9 +388,9 @@
 	for (i = 7; i >= 0; i--) {
 		tmp = (fwh_conf >> (i + 0x8)) & 0x1;
 		msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
-			     (0x1ff8 + i) * 0x80000,
-			     (0x1ff0 + i) * 0x80000,
-			     tmp ? "en" : "dis");
+			 (0x1ff8 + i) * 0x80000,
+			 (0x1ff0 + i) * 0x80000,
+			 tmp ? "en" : "dis");
 		if ((tmp == 1) && contiguous) {
 			max_decode_fwh_decode = (8 - i) * 0x80000;
 		} else {
@@ -399,9 +400,9 @@
 	for (i = 3; i >= 0; i--) {
 		tmp = (fwh_conf >> i) & 0x1;
 		msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
-			     (0xff4 + i) * 0x100000,
-			     (0xff0 + i) * 0x100000,
-			     tmp ? "en" : "dis");
+			 (0xff4 + i) * 0x100000,
+			 (0xff0 + i) * 0x100000,
+			 tmp ? "en" : "dis");
 		if ((tmp == 1) && contiguous) {
 			max_decode_fwh_decode = (8 - i) * 0x100000;
 		} else {
@@ -420,25 +421,24 @@
 
 static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
 {
-       uint16_t old, new;
-       int err;
+	uint16_t old, new;
+	int err;
 
-       if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
-               return err;
+	if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
+		return err;
 
-       old = pci_read_byte(dev, 0xd9);
-       msg_pdbg("BIOS Prefetch Enable: %sabled, ",
-                    (old & 1) ? "en" : "dis");
-       new = old & ~1;
+	old = pci_read_byte(dev, 0xd9);
+	msg_pdbg("BIOS Prefetch Enable: %sabled, ",
+		 (old & 1) ? "en" : "dis");
+	new = old & ~1;
 
-       if (new != old)
-               rpci_write_byte(dev, 0xd9, new);
+	if (new != old)
+		rpci_write_byte(dev, 0xd9, new);
 
 	buses_supported = BUS_FWH;
-       return 0;
+	return 0;
 }
 
-
 #define ICH_STRAP_RSVD 0x00
 #define ICH_STRAP_SPI  0x01
 #define ICH_STRAP_PCI  0x02
@@ -457,8 +457,12 @@
 	uint8_t bbs, buc;
 	uint32_t tmp, gcs;
 	void *rcrb;
-	//TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
-	//static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
+
+	/*
+	 * TODO: These names are incorrect for EP80579. For that, the solution
+	 * would look like the commented line below.
+	 */
+	// static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
 	static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
 
 	/* Enable Flash Writes */
@@ -474,13 +478,13 @@
 	gcs = mmio_readl(rcrb + 0x3410);
 	msg_pdbg("GCS = 0x%x: ", gcs);
 	msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
-		     (gcs & 0x1) ? "en" : "dis");
+		 (gcs & 0x1) ? "en" : "dis");
 	bbs = (gcs >> 10) & 0x3;
 	msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
 
 	buc = mmio_readb(rcrb + 0x3414);
 	msg_pdbg("Top Swap : %s\n",
-		     (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
+		 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
 
 	/* It seems the ICH7 does not support SPI and LPC chips at the same
 	 * time. At least not with our current code. So we prevent searching
@@ -489,20 +493,20 @@
 
 	buses_supported = BUS_FWH;
 	if (ich_generation == 7) {
-		if(bbs == ICH_STRAP_LPC) {
+		if (bbs == ICH_STRAP_LPC) {
 			/* No further SPI initialization required */
 			return ret;
-		}
-		else
+		} else {
 			/* Disable LPC/FWH if strapped to PCI or SPI */
 			buses_supported = 0;
+		}
 	}
 
-	/* this adds BUS_SPI */
+	/* This adds BUS_SPI */
 	if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
-	        if (!ret)
-		        ret = ERROR_NONFATAL;
-        }
+		if (!ret)
+			ret = ERROR_NONFATAL;
+	}
 
 	return ret;
 }
@@ -532,8 +536,7 @@
 	uint8_t val;
 
 	val = pci_read_byte(dev, 0x71);
-	if (val & 0x40)
-	{
+	if (val & 0x40) {
 		msg_pdbg("Disabling byte merging\n");
 		val &= ~0x40;
 		rpci_write_byte(dev, 0x71, val);
@@ -545,7 +548,7 @@
 {
 	uint8_t val;
 
-	/* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
+	/* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
 	rpci_write_byte(dev, 0x41, 0x7f);
 
 	/* ROM write enable */
@@ -555,15 +558,15 @@
 
 	if (pci_read_byte(dev, 0x40) != val) {
 		msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
-		       name);
+			  name);
 		return -1;
 	}
 
 	if (dev->device_id == 0x3227) { /* VT8237R */
-	    /* All memory cycles, not just ROM ones, go to LPC. */
-	    val = pci_read_byte(dev, 0x59);
-	    val &= ~0x80;
-	    rpci_write_byte(dev, 0x59, val);
+		/* All memory cycles, not just ROM ones, go to LPC. */
+		val = pci_read_byte(dev, 0x59);
+		val &= ~0x80;
+		rpci_write_byte(dev, 0x59, val);
 	}
 
 	return 0;
@@ -671,7 +674,8 @@
 	new = pci_read_byte(dev, 0x52);
 
 	if (new != 0xee) {
-		msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
+		msg_pinfo("tried to set register 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY)\n", 0x52, new, name);
 		return -1;
 	}
 
@@ -689,7 +693,8 @@
 	if (new != old) {
 		rpci_write_byte(dev, 0x43, new);
 		if (pci_read_byte(dev, 0x43) != new) {
-			msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
+			msg_pinfo("tried to set 0x%x to 0x%x on %s failed "
+				  "(WARNING ONLY)\n", 0x43, new, name);
 		}
 	}
 
@@ -701,7 +706,8 @@
 	rpci_write_byte(dev, 0x40, new);
 
 	if (pci_read_byte(dev, 0x40) != new) {
-		msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
+		msg_pinfo("tried to set 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY)\n", 0x40, new, name);
 		return -1;
 	}
 
@@ -721,19 +727,19 @@
 		if ((prot & 0x3) == 0)
 			continue;
 		msg_pinfo("SB600 %s%sprotected from 0x%08x to 0x%08x\n",
-			(prot & 0x1) ? "write " : "",
-			(prot & 0x2) ? "read " : "",
-			(prot & 0xfffff800),
-			(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
+			  (prot & 0x1) ? "write " : "",
+			  (prot & 0x2) ? "read " : "",
+			  (prot & 0xfffff800),
+			  (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
 		prot &= 0xfffffffc;
 		rpci_write_byte(dev, reg, prot);
 		prot = pci_read_long(dev, reg);
 		if (prot & 0x3)
 			msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n",
-				(prot & 0x1) ? "write " : "",
-				(prot & 0x2) ? "read " : "",
-				(prot & 0xfffff800),
-				(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
+				 (prot & 0x1) ? "write " : "",
+				 (prot & 0x2) ? "read " : "",
+				 (prot & 0xfffff800),
+				 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
 	}
 
 	buses_supported = BUS_LPC | BUS_FWH;
@@ -800,7 +806,8 @@
 	if (new != old) {
 		rpci_write_byte(dev, 0x88, new);
 		if (pci_read_byte(dev, 0x88) != new) {
-			msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
+			msg_pinfo("tried to set 0x%x to 0x%x on %s failed "
+				  "(WARNING ONLY)\n", 0x88, new, name);
 		}
 	}
 
@@ -811,7 +818,8 @@
 	rpci_write_byte(dev, 0x6d, new);
 
 	if (pci_read_byte(dev, 0x6d) != new) {
-		msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
+		msg_pinfo("tried to set 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY)\n", 0x6d, new, name);
 		return -1;
 	}
 
@@ -894,7 +902,8 @@
 	rpci_write_byte(dev, 0x6d, new);
 
 	if (pci_read_byte(dev, 0x6d) != new) {
-		msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
+		msg_pinfo("tried to set 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY)\n", 0x6d, new, name);
 		return -1;
 	}
 
@@ -908,8 +917,7 @@
  */
 static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
 {
-	int ret = 0;
-	int want_spi = 0;
+	int ret = 0, want_spi = 0;
 	uint8_t val;
 
 	msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
@@ -952,9 +960,9 @@
 	rpci_write_byte(dev, 0x8a, val);
 #endif
 
-	if (mcp6x_spi_init(want_spi)) {
+	if (mcp6x_spi_init(want_spi))
 		ret = 1;
-	}
+
 out_msg:
 	msg_pinfo("Please send the output of \"flashrom -V\" to "
 		  "flashrom@flashrom.org with\n"
@@ -1020,7 +1028,8 @@
 			flashbase = parx << 12;
 		}
 	} else {
-		msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
+		msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
+			  "Assuming flash at 4G\n");
 	}
 
 	/* 4. Clean up */
@@ -1269,9 +1278,9 @@
 			msg_pinfo("OK - searching further chips.\n");
 		} else if (ret < 0)
 			msg_pinfo("FAILED!\n");
-		else if(ret == 0)
+		else if (ret == 0)
 			msg_pinfo("OK.\n");
-		else if(ret == ERROR_NONFATAL)
+		else if (ret == ERROR_NONFATAL)
 			msg_pinfo("PROBLEMS, continuing anyway\n");
 	}
 
diff --git a/cli_classic.c b/cli_classic.c
index 36fe9ad..22711b0 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -103,45 +103,37 @@
 	const struct flashchip *flash;
 	struct flashchip flashes[3];
 	struct flashchip *fill_flash;
-	int startchip = 0;
-	int chipcount = 0;
 	const char *name;
-	int namelen;
-	int opt;
-	int option_index = 0;
-	int force = 0;
+	int startchip = 0, chipcount = 0, namelen, opt, option_index = 0;
 	int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0;
-	int dont_verify_it = 0, list_supported = 0;
+	int dont_verify_it = 0, list_supported = 0, force = 0;
 #if CONFIG_PRINT_WIKI == 1
 	int list_supported_wiki = 0;
 #endif
-	int operation_specified = 0;
-	int i;
-	int ret = 0;
+	int operation_specified = 0, i, ret = 0;
 
 	static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh";
 	static const struct option long_options[] = {
-		{"read", 1, NULL, 'r'},
-		{"write", 1, NULL, 'w'},
-		{"erase", 0, NULL, 'E'},
-		{"verify", 1, NULL, 'v'},
-		{"noverify", 0, NULL, 'n'},
-		{"chip", 1, NULL, 'c'},
-		{"mainboard", 1, NULL, 'm'},
-		{"verbose", 0, NULL, 'V'},
-		{"force", 0, NULL, 'f'},
-		{"layout", 1, NULL, 'l'},
-		{"image", 1, NULL, 'i'},
-		{"list-supported", 0, NULL, 'L'},
-		{"list-supported-wiki", 0, NULL, 'z'},
-		{"programmer", 1, NULL, 'p'},
-		{"help", 0, NULL, 'h'},
-		{"version", 0, NULL, 'R'},
-		{NULL, 0, NULL, 0}
+		{"read",		1, NULL, 'r'},
+		{"write",		1, NULL, 'w'},
+		{"erase",		0, NULL, 'E'},
+		{"verify",		1, NULL, 'v'},
+		{"noverify",		0, NULL, 'n'},
+		{"chip",		1, NULL, 'c'},
+		{"mainboard",		1, NULL, 'm'},
+		{"verbose",		0, NULL, 'V'},
+		{"force",		0, NULL, 'f'},
+		{"layout",		1, NULL, 'l'},
+		{"image",		1, NULL, 'i'},
+		{"list-supported",	0, NULL, 'L'},
+		{"list-supported-wiki",	0, NULL, 'z'},
+		{"programmer",		1, NULL, 'p'},
+		{"help",		0, NULL, 'h'},
+		{"version",		0, NULL, 'R'},
+		{NULL,			0, NULL, 0},
 	};
 
 	char *filename = NULL;
-
 	char *tempstr = NULL;
 	char *pparam = NULL;
 
@@ -355,7 +347,7 @@
 			fprintf(stderr, "Error: Unknown chip '%s' specified.\n",
 				chip_to_probe);
 			printf("Run flashrom -L to view the hardware supported "
-				"in this flashrom version.\n");
+			       "in this flashrom version.\n");
 			exit(1);
 		}
 		/* Clean up after the check. */
@@ -384,23 +376,28 @@
 			flashes[0].name);
 		for (i = 1; i < chipcount; i++)
 			printf(", \"%s\"", flashes[i].name);
-		printf("\nPlease specify which chip to use with the -c <chipname> option.\n");
+		printf("\nPlease specify which chip to use with the "
+		       "-c <chipname> option.\n");
 		ret = 1;
 		goto out_shutdown;
 	} else if (!chipcount) {
 		printf("No EEPROM/flash device found.\n");
 		if (!force || !chip_to_probe) {
-			printf("Note: flashrom can never write if the flash chip isn't found automatically.\n");
+			printf("Note: flashrom can never write if the flash "
+			       "chip isn't found automatically.\n");
 		}
 		if (force && read_it && chip_to_probe) {
-			printf("Force read (-f -r -c) requested, pretending the chip is there:\n");
+			printf("Force read (-f -r -c) requested, pretending "
+			       "the chip is there:\n");
 			startchip = probe_flash(0, &flashes[0], 1);
 			if (startchip == -1) {
-				printf("Probing for flash chip '%s' failed.\n", chip_to_probe);
+				printf("Probing for flash chip '%s' failed.\n",
+				       chip_to_probe);
 				ret = 1;
 				goto out_shutdown;
 			}
-			printf("Please note that forced reads most likely contain garbage.\n");
+			printf("Please note that forced reads most likely "
+			       "contain garbage.\n");
 			return read_flash_to_file(&flashes[0], filename);
 		}
 		ret = 1;
diff --git a/dediprog.c b/dediprog.c
index 1cbde18..d752fb4 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -71,7 +71,7 @@
 static int dediprog_set_leds(int leds)
 {
 	int ret, target_leds;
-	
+
 	if (leds < 0 || leds > 7)
 		leds = 0; // Bogus value, enable all LEDs
 
@@ -92,9 +92,11 @@
 		target_leds = leds;
 	}
 
-	ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, target_leds, NULL, 0x0, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, target_leds,
+			      NULL, 0x0, DEFAULT_TIMEOUT);
 	if (ret != 0x0) {
-		msg_perr("Command Set LED 0x%x failed (%s)!\n", leds, usb_strerror());
+		msg_perr("Command Set LED 0x%x failed (%s)!\n",
+			 leds, usb_strerror());
 		return 1;
 	}
 
@@ -129,9 +131,11 @@
 	msg_pdbg("Setting SPI voltage to %u.%03u V\n", millivolt / 1000,
 		 millivolt % 1000);
 
-	ret = usb_control_msg(dediprog_handle, 0x42, 0x9, voltage_selector, 0xff, NULL, 0x0, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0x42, 0x9, voltage_selector,
+			      0xff, NULL, 0x0, DEFAULT_TIMEOUT);
 	if (ret != 0x0) {
-		msg_perr("Command Set SPI Voltage 0x%x failed!\n", voltage_selector);
+		msg_perr("Command Set SPI Voltage 0x%x failed!\n",
+			 voltage_selector);
 		return 1;
 	}
 	return 0;
@@ -186,7 +190,8 @@
 	}
 	msg_pdbg("Setting SPI speed to %u kHz\n", khz);
 
-	ret = usb_control_msg(dediprog_handle, 0x42, 0x61, speed, 0xff, NULL, 0x0, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0x42, 0x61, speed, 0xff, NULL,
+			      0x0, DEFAULT_TIMEOUT);
 	if (ret != 0x0) {
 		msg_perr("Command Set SPI Speed 0x%x failed!\n", speed);
 		return 1;
@@ -248,7 +253,8 @@
 	return 0;
 }
 
-static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start,
+			     int len)
 {
 	int ret;
 	/* chunksize must be 512, other sizes will NOT work at all. */
@@ -293,7 +299,8 @@
 	return 0;
 }
 
-static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf,
+				  int start, int len)
 {
 	int ret;
 
@@ -327,7 +334,9 @@
 		return 1;
 	}
 	
-	ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff,
+			      readcnt ? 0x1 : 0x0, (char *)writearr, writecnt,
+			      DEFAULT_TIMEOUT);
 	if (ret != writecnt) {
 		msg_perr("Send SPI failed, expected %i, got %i %s!\n",
 			 writecnt, ret, usb_strerror());
@@ -336,7 +345,8 @@
 	if (!readcnt)
 		return 0;
 	memset(readarr, 0, readcnt);
-	ret = usb_control_msg(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, (char *)readarr, readcnt, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000,
+			     (char *)readarr, readcnt, DEFAULT_TIMEOUT);
 	if (ret != readcnt) {
 		msg_perr("Receive SPI failed, expected %i, got %i %s!\n",
 			 readcnt, ret, usb_strerror());
@@ -353,7 +363,8 @@
 
 	/* Command Prepare Receive Device String. */
 	memset(buf, 0, sizeof(buf));
-	ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef03, buf, 0x1, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef03, buf,
+			      0x1, DEFAULT_TIMEOUT);
 	/* The char casting is needed to stop gcc complaining about an always true comparison. */
 	if ((ret != 0x1) || (buf[0] != (char)0xff)) {
 		msg_perr("Unexpected response to Command Prepare Receive Device"
@@ -362,7 +373,8 @@
 	}
 	/* Command Receive Device String. */
 	memset(buf, 0, sizeof(buf));
-	ret = usb_control_msg(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf, 0x10, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf,
+			      0x10, DEFAULT_TIMEOUT);
 	if (ret != 0x10) {
 		msg_perr("Incomplete/failed Command Receive Device String!\n");
 		return 1;
@@ -397,7 +409,8 @@
 	char buf[0x1];
 
 	memset(buf, 0, sizeof(buf));
-	ret = usb_control_msg(dediprog_handle, 0xc3, 0xb, 0x0, 0x0, buf, 0x1, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0xc3, 0xb, 0x0, 0x0, buf,
+			      0x1, DEFAULT_TIMEOUT);
 	if (ret < 0) {
 		msg_perr("Command A failed (%s)!\n", usb_strerror());
 		return 1;
@@ -420,7 +433,8 @@
 	char buf[0x3];
 
 	memset(buf, 0, sizeof(buf));
-	ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef00, buf, 0x3, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef00, buf,
+			      0x3, DEFAULT_TIMEOUT);
 	if (ret < 0) {
 		msg_perr("Command B failed (%s)!\n", usb_strerror());
 		return 1;
@@ -444,7 +458,8 @@
 {
 	int ret;
 
-	ret = usb_control_msg(dediprog_handle, 0x42, 0x4, 0x0, 0x0, NULL, 0x0, DEFAULT_TIMEOUT);
+	ret = usb_control_msg(dediprog_handle, 0x42, 0x4, 0x0, 0x0, NULL,
+			      0x0, DEFAULT_TIMEOUT);
 	if (ret != 0x0) {
 		msg_perr("Command C failed (%s)!\n", usb_strerror());
 		return 1;
@@ -464,7 +479,8 @@
 	char buf[0x1];
 
 	memset(buf, 0, sizeof(buf));
-	ret = usb_control_msg(dediprog_handle, 0xc2, 0x11, 0xff, 0xff, buf, 0x1, timeout);
+	ret = usb_control_msg(dediprog_handle, 0xc2, 0x11, 0xff, 0xff, buf,
+			      0x1, timeout);
 	/* This check is most probably wrong. Command F always causes a timeout
 	 * in the logs, so we should check for timeout instead of checking for
 	 * success.
@@ -480,9 +496,7 @@
 static int parse_voltage(char *voltage)
 {
 	char *tmp = NULL;
-	int i;
-	int millivolt;
-	int fraction = 0;
+	int i, millivolt, fraction = 0;
 
 	if (!voltage || !strlen(voltage)) {
 		msg_perr("Empty voltage= specified.\n");
@@ -527,13 +541,13 @@
 }
 
 static const struct spi_programmer spi_programmer_dediprog = {
-	.type = SPI_CONTROLLER_DEDIPROG,
-	.max_data_read = MAX_DATA_UNSPECIFIED,
-	.max_data_write = MAX_DATA_UNSPECIFIED,
-	.command = dediprog_spi_send_command,
-	.multicommand = default_spi_send_multicommand,
-	.read = dediprog_spi_read,
-	.write_256 = dediprog_spi_write_256,
+	.type		= SPI_CONTROLLER_DEDIPROG,
+	.max_data_read	= MAX_DATA_UNSPECIFIED,
+	.max_data_write	= MAX_DATA_UNSPECIFIED,
+	.command	= dediprog_spi_send_command,
+	.multicommand	= default_spi_send_multicommand,
+	.read		= dediprog_spi_read,
+	.write_256	= dediprog_spi_write_256,
 };
 
 static int dediprog_shutdown(void *data)
@@ -560,8 +574,7 @@
 {
 	struct usb_device *dev;
 	char *voltage;
-	int millivolt = 3500;
-	int ret;
+	int millivolt = 3500, ret;
 
 	msg_pspew("%s\n", __func__);
 
@@ -569,9 +582,8 @@
 	if (voltage) {
 		millivolt = parse_voltage(voltage);
 		free(voltage);
-		if (millivolt < 0) {
+		if (millivolt < 0)
 			return 1;
-		}
 		msg_pinfo("Setting voltage to %i mV\n", millivolt);
 	}
 
@@ -585,8 +597,7 @@
 		return 1;
 	}
 	msg_pdbg("Found USB device (%04x:%04x).\n",
-		 dev->descriptor.idVendor,
-		 dev->descriptor.idProduct);
+		 dev->descriptor.idVendor, dev->descriptor.idProduct);
 	dediprog_handle = usb_open(dev);
 	ret = usb_set_configuration(dediprog_handle, 1);
 	if (ret < 0) {
@@ -666,7 +677,8 @@
 	/* JEDEC RDID */
 	msg_pdbg("Sending RDID\n");
 	buf[0] = JEDEC_RDID;
-	if (dediprog_spi_send_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, (unsigned char *)buf, (unsigned char *)buf))
+	if (dediprog_spi_send_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE,
+				(unsigned char *)buf, (unsigned char *)buf))
 		return 1;
 	msg_pdbg("Receiving response: ");
 	print_hex(buf, JEDEC_RDID_INSIZE);
diff --git a/dmi.c b/dmi.c
index 3b17b11..4f36245 100644
--- a/dmi.c
+++ b/dmi.c
@@ -107,13 +107,14 @@
 	}
 
 	/* Kill lines starting with '#', as recent dmidecode versions
-	   have the quirk to emit a "# SMBIOS implementations newer..."
-	   message even on "-s" if the SMBIOS declares a
-	   newer-than-supported version number, while it *should* only print
-	   the requested string. */
+	 * have the quirk to emit a "# SMBIOS implementations newer..."
+	 * message even on "-s" if the SMBIOS declares a
+	 * newer-than-supported version number, while it *should* only print
+	 * the requested string.
+	 */
 	do {
 		if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) {
-			if(ferror(dmidecode_pipe)) {
+			if (ferror(dmidecode_pipe)) {
 				msg_perr("DMI pipe read error\n");
 				pclose(dmidecode_pipe);
 				return NULL;
@@ -121,7 +122,7 @@
 				answerbuf[0] = 0;	/* Hit EOF */
 			}
 		}
-	} while(answerbuf[0] == '#');
+	} while (answerbuf[0] == '#');
 
 	/* Toss all output above DMI_MAX_ANSWER_LEN away to prevent
 	   deadlock on pclose. */
@@ -129,13 +130,12 @@
 		getc(dmidecode_pipe);
 	if (pclose(dmidecode_pipe) != 0) {
 		msg_pinfo("dmidecode execution unsuccessful - continuing "
-			"without DMI info\n");
+			  "without DMI info\n");
 		return NULL;
 	}
 
 	/* Chomp trailing newline. */
-	if (answerbuf[0] != 0 &&
-	    answerbuf[strlen(answerbuf) - 1] == '\n')
+	if (answerbuf[0] != 0 && answerbuf[strlen(answerbuf) - 1] == '\n')
 		answerbuf[strlen(answerbuf) - 1] = 0;
 	msg_pdbg("DMI string %s: \"%s\"\n", string_name, answerbuf);
 
@@ -196,8 +196,7 @@
  */
 static int dmi_compare(const char *value, const char *pattern)
 {
-	int anchored = 0;
-	int patternlen;
+	int anchored = 0, patternlen;
 
 	msg_pspew("matching %s against %s\n", value, pattern);
 	/* The empty string is part of all strings! */
diff --git a/drkaiser.c b/drkaiser.c
index be8e5cb..b11d845 100644
--- a/drkaiser.c
+++ b/drkaiser.c
@@ -58,7 +58,7 @@
 
 	/* Write magic register to enable flash write. */
 	rpci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR,
-		       PCI_MAGIC_DRKAISER_VALUE);
+			PCI_MAGIC_DRKAISER_VALUE);
 
 	/* Map 128kB flash memory window. */
 	drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
diff --git a/dummyflasher.c b/dummyflasher.c
index 4d0b42e..be8f552 100644
--- a/dummyflasher.c
+++ b/dummyflasher.c
@@ -62,16 +62,17 @@
 
 static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
 		      const unsigned char *writearr, unsigned char *readarr);
-static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
+static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf,
+			       int start, int len);
 
 static const struct spi_programmer spi_programmer_dummyflasher = {
-	.type = SPI_CONTROLLER_DUMMY,
-	.max_data_read = MAX_DATA_READ_UNLIMITED,
-	.max_data_write = MAX_DATA_UNSPECIFIED,
-	.command = dummy_spi_send_command,
-	.multicommand = default_spi_send_multicommand,
-	.read = default_spi_read,
-	.write_256 = dummy_spi_write_256,
+	.type		= SPI_CONTROLLER_DUMMY,
+	.max_data_read	= MAX_DATA_READ_UNLIMITED,
+	.max_data_write	= MAX_DATA_UNSPECIFIED,
+	.command	= dummy_spi_send_command,
+	.multicommand	= default_spi_send_multicommand,
+	.read		= default_spi_read,
+	.write_256	= dummy_spi_write_256,
 };
 
 static int dummy_shutdown(void *data)
@@ -520,14 +521,14 @@
 	}
 #endif
 	msg_pspew(" reading %u bytes:", readcnt);
-	for (i = 0; i < readcnt; i++) {
+	for (i = 0; i < readcnt; i++)
 		msg_pspew(" 0x%02x", readarr[i]);
-	}
 	msg_pspew("\n");
 	return 0;
 }
 
-static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf,
+			       int start, int len)
 {
 	return spi_write_chunked(flash, buf, start, len,
 				 spi_write_256_chunksize);
diff --git a/flashrom.c b/flashrom.c
index 0a1d812..07cfdd9 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -182,38 +182,38 @@
 #if CONFIG_NICREALTEK == 1
 	{
 		/* This programmer works for Realtek RTL8139 and SMC 1211. */
-		.name                   = "nicrealtek",
-		//.name                   = "nicsmc1211",
-		.init                   = nicrealtek_init,
-		.map_flash_region       = fallback_map,
-		.unmap_flash_region     = fallback_unmap,
-		.chip_readb             = nicrealtek_chip_readb,
-		.chip_readw             = fallback_chip_readw,
-		.chip_readl             = fallback_chip_readl,
-		.chip_readn             = fallback_chip_readn,
-		.chip_writeb            = nicrealtek_chip_writeb,
-		.chip_writew            = fallback_chip_writew,
-		.chip_writel            = fallback_chip_writel,
-		.chip_writen            = fallback_chip_writen,
-		.delay                  = internal_delay,
+		.name			= "nicrealtek",
+		//.name			= "nicsmc1211",
+		.init			= nicrealtek_init,
+		.map_flash_region	= fallback_map,
+		.unmap_flash_region	= fallback_unmap,
+		.chip_readb		= nicrealtek_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= nicrealtek_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+		.delay			= internal_delay,
 	},
 #endif
 
 #if CONFIG_NICNATSEMI == 1
 	{
-		.name                   = "nicnatsemi",
-		.init                   = nicnatsemi_init,
-		.map_flash_region       = fallback_map,
-		.unmap_flash_region     = fallback_unmap,
-		.chip_readb             = nicnatsemi_chip_readb,
-		.chip_readw             = fallback_chip_readw,
-		.chip_readl             = fallback_chip_readl,
-		.chip_readn             = fallback_chip_readn,
-		.chip_writeb            = nicnatsemi_chip_writeb,
-		.chip_writew            = fallback_chip_writew,
-		.chip_writel            = fallback_chip_writel,
-		.chip_writen            = fallback_chip_writen,
-		.delay                  = internal_delay,
+		.name			= "nicnatsemi",
+		.init			= nicnatsemi_init,
+		.map_flash_region	= fallback_map,
+		.unmap_flash_region	= fallback_unmap,
+		.chip_readb		= nicnatsemi_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= nicnatsemi_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+		.delay			= internal_delay,
 	},
 #endif
 
@@ -399,37 +399,37 @@
 
 #if CONFIG_NICINTEL_SPI == 1
 	{
-		.name = "nicintel_spi",
-		.init = nicintel_spi_init,
-		.map_flash_region = fallback_map,
-		.unmap_flash_region = fallback_unmap,
-		.chip_readb = noop_chip_readb,
-		.chip_readw = fallback_chip_readw,
-		.chip_readl = fallback_chip_readl,
-		.chip_readn = fallback_chip_readn,
-		.chip_writeb = noop_chip_writeb,
-		.chip_writew = fallback_chip_writew,
-		.chip_writel = fallback_chip_writel,
-		.chip_writen = fallback_chip_writen,
-		.delay = internal_delay,
+		.name			= "nicintel_spi",
+		.init			= nicintel_spi_init,
+		.map_flash_region	= fallback_map,
+		.unmap_flash_region	= fallback_unmap,
+		.chip_readb		= noop_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= noop_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+		.delay			= internal_delay,
 	},
 #endif
 
 #if CONFIG_OGP_SPI == 1
 	{
-		.name = "ogp_spi",
-		.init = ogp_spi_init,
-		.map_flash_region = fallback_map,
-		.unmap_flash_region = fallback_unmap,
-		.chip_readb = noop_chip_readb,
-		.chip_readw = fallback_chip_readw,
-		.chip_readl = fallback_chip_readl,
-		.chip_readn = fallback_chip_readn,
-		.chip_writeb = noop_chip_writeb,
-		.chip_writew = fallback_chip_writew,
-		.chip_writel = fallback_chip_writel,
-		.chip_writen = fallback_chip_writen,
-		.delay = internal_delay,
+		.name			= "ogp_spi",
+		.init			= ogp_spi_init,
+		.map_flash_region	= fallback_map,
+		.unmap_flash_region	= fallback_unmap,
+		.chip_readb		= noop_chip_readb,
+		.chip_readw		= fallback_chip_readw,
+		.chip_readl		= fallback_chip_readl,
+		.chip_readn		= fallback_chip_readn,
+		.chip_writeb		= noop_chip_writeb,
+		.chip_writew		= fallback_chip_writew,
+		.chip_writel		= fallback_chip_writel,
+		.chip_writen		= fallback_chip_writen,
+		.delay			= internal_delay,
 	},
 #endif
 
@@ -503,7 +503,7 @@
 		.parallel	= 0xffffffff,
 		.lpc		= 0xffffffff,
 		.fwh		= 0xffffffff,
-		.spi		= 0xffffffff
+		.spi		= 0xffffffff,
 	};
 	buses_supported = BUS_NONE;
 	/* Default to top aligned flash at 4 GB. */
@@ -600,13 +600,14 @@
 	size_t size = flash->total_size * 1024;
 	/* Flash registers live 4 MByte below the flash. */
 	/* FIXME: This is incorrect for nonstandard flashbase. */
-	flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size);
+	flash->virtual_registers = (chipaddr)programmer_map_flash_region(
+	    "flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size);
 }
 
 int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len)
 {
 	chip_readn(buf, flash->virtual_memory + start, len);
-		
+
 	return 0;
 }
 
@@ -685,7 +686,7 @@
 		param_pos++;
 		param_pos = strstr(param_pos, needle);
 	} while (1);
-	
+
 	if (param_pos) {
 		/* Get the string after needle and '='. */
 		opt_pos = param_pos + needlelen + 1;
@@ -743,17 +744,17 @@
 
 /*
  * @cmpbuf	buffer to compare against, cmpbuf[0] is expected to match the
-		flash content at location start
+ *		flash content at location start
  * @start	offset to the base address of the flash chip
  * @len		length of the verified area
  * @message	string to print in the "FAILED" message
  * @return	0 for success, -1 for failure
  */
-int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message)
+int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len,
+		 const char *message)
 {
-	int i, ret = 0;
+	int i, ret = 0, failcount = 0;
 	uint8_t *readbuf = malloc(len);
-	int failcount = 0;
 
 	if (!len)
 		goto out_free;
@@ -776,7 +777,7 @@
 	}
 	if (!message)
 		message = "VERIFY";
-	
+
 	ret = flash->read(flash, readbuf, start, len);
 	if (ret) {
 		msg_gerr("Verification impossible because read failed "
@@ -796,7 +797,7 @@
 	}
 	if (failcount) {
 		msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n",
-			start, start + len - 1, failcount);
+			 start, start + len - 1, failcount);
 		ret = -1;
 	}
 
@@ -831,8 +832,7 @@
  */
 int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran)
 {
-	int result = 0;
-	int i, j, limit;
+	int result = 0, i, j, limit;
 
 	switch (gran) {
 	case write_gran_1bit:
@@ -898,8 +898,7 @@
 static int get_next_write(uint8_t *have, uint8_t *want, int len,
 			  int *first_start, enum write_granularity gran)
 {
-	int need_write = 0, rel_start = 0, first_len = 0;
-	int i, limit, stride;
+	int need_write = 0, rel_start = 0, first_len = 0, i, limit, stride;
 
 	switch (gran) {
 	case write_gran_1bit:
@@ -1080,38 +1079,38 @@
 int check_max_decode(enum chipbustype buses, uint32_t size)
 {
 	int limitexceeded = 0;
-	if ((buses & BUS_PARALLEL) &&
-	    (max_rom_decode.parallel < size)) {
+
+	if ((buses & BUS_PARALLEL) && (max_rom_decode.parallel < size)) {
 		limitexceeded++;
 		msg_pdbg("Chip size %u kB is bigger than supported "
-			     "size %u kB of chipset/board/programmer "
-			     "for %s interface, "
-			     "probe/read/erase/write may fail. ", size / 1024,
-			     max_rom_decode.parallel / 1024, "Parallel");
+			 "size %u kB of chipset/board/programmer "
+			 "for %s interface, "
+			 "probe/read/erase/write may fail. ", size / 1024,
+			 max_rom_decode.parallel / 1024, "Parallel");
 	}
 	if ((buses & BUS_LPC) && (max_rom_decode.lpc < size)) {
 		limitexceeded++;
 		msg_pdbg("Chip size %u kB is bigger than supported "
-			     "size %u kB of chipset/board/programmer "
-			     "for %s interface, "
-			     "probe/read/erase/write may fail. ", size / 1024,
-			     max_rom_decode.lpc / 1024, "LPC");
+			 "size %u kB of chipset/board/programmer "
+			 "for %s interface, "
+			 "probe/read/erase/write may fail. ", size / 1024,
+			 max_rom_decode.lpc / 1024, "LPC");
 	}
 	if ((buses & BUS_FWH) && (max_rom_decode.fwh < size)) {
 		limitexceeded++;
 		msg_pdbg("Chip size %u kB is bigger than supported "
-			     "size %u kB of chipset/board/programmer "
-			     "for %s interface, "
-			     "probe/read/erase/write may fail. ", size / 1024,
-			     max_rom_decode.fwh / 1024, "FWH");
+			 "size %u kB of chipset/board/programmer "
+			 "for %s interface, "
+			 "probe/read/erase/write may fail. ", size / 1024,
+			 max_rom_decode.fwh / 1024, "FWH");
 	}
 	if ((buses & BUS_SPI) && (max_rom_decode.spi < size)) {
 		limitexceeded++;
 		msg_pdbg("Chip size %u kB is bigger than supported "
-			     "size %u kB of chipset/board/programmer "
-			     "for %s interface, "
-			     "probe/read/erase/write may fail. ", size / 1024,
-			     max_rom_decode.spi / 1024, "SPI");
+			 "size %u kB of chipset/board/programmer "
+			 "for %s interface, "
+			 "probe/read/erase/write may fail. ", size / 1024,
+			 max_rom_decode.spi / 1024, "SPI");
 	}
 	if (!limitexceeded)
 		return 0;
@@ -1121,8 +1120,8 @@
 	if (bitcount(buses) > limitexceeded)
 		/* FIXME: This message is designed towards CLI users. */
 		msg_pdbg("There is at least one common chip/programmer "
-			     "interface which can support a chip of this size. "
-			     "You can try --force at your own risk.\n");
+			 "interface which can support a chip of this size. "
+			 "You can try --force at your own risk.\n");
 	return 1;
 }
 
@@ -1232,7 +1231,8 @@
 	return ret;
 }
 
-int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename)
+int read_buf_from_file(unsigned char *buf, unsigned long size,
+		       const char *filename)
 {
 	unsigned long numbytes;
 	FILE *image;
@@ -1265,7 +1265,8 @@
 	return 0;
 }
 
-int write_buf_to_file(unsigned char *buf, unsigned long size, const char *filename)
+int write_buf_to_file(unsigned char *buf, unsigned long size,
+		      const char *filename)
 {
 	unsigned long numbytes;
 	FILE *image;
@@ -1325,8 +1326,7 @@
  */
 static int selfcheck_eraseblocks(const struct flashchip *flash)
 {
-	int i, j, k;
-	int ret = 0;
+	int i, j, k, ret = 0;
 
 	for (k = 0; k < NUM_ERASEFUNCTIONS; k++) {
 		unsigned int done = 0;
@@ -1357,7 +1357,7 @@
 		/* Empty eraseblock definition with erase function.  */
 		if (!done && eraser.block_erase)
 			msg_gspew("Strange: Empty eraseblock definition with "
-				"non-empty erase function. Not an error.\n");
+				  "non-empty erase function. Not an error.\n");
 		if (!done)
 			continue;
 		if (done != flash->total_size * 1024) {
@@ -1396,11 +1396,7 @@
 							unsigned int addr,
 							unsigned int len))
 {
-	int starthere = 0;
-	int lenhere = 0;
-	int ret = 0;
-	int skip = 1;
-	int writecount = 0;
+	int starthere = 0, lenhere = 0, ret = 0, skip = 1, writecount = 0;
 	enum write_granularity gran = write_gran_256bytes; /* FIXME */
 
 	/* curcontents and newcontents are opaque to walk_eraseregions, and
@@ -1455,9 +1451,9 @@
 			     void *param1, void *param2)
 {
 	int i, j;
-	unsigned int start = 0;
-	unsigned int len;
+	unsigned int start = 0, len;
 	struct block_eraser eraser = flash->block_erasers[erasefunction];
+
 	for (i = 0; i < NUM_ERASEREGIONS; i++) {
 		/* count==0 for all automatically initialized array
 		 * members so the loop below won't be executed for them.
@@ -1504,7 +1500,8 @@
 	return 0;
 }
 
-int erase_and_write_flash(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents)
+int erase_and_write_flash(struct flashchip *flash, uint8_t *oldcontents,
+			  uint8_t *newcontents)
 {
 	int k, ret = 1;
 	uint8_t *curcontents;
@@ -1591,7 +1588,7 @@
 		"DO NOT REBOOT OR POWEROFF!\n");
 }
 
-/* The way to go if you want a delimited list of programmers*/
+/* The way to go if you want a delimited list of programmers */
 void list_programmers(const char *delim)
 {
 	enum programmer p;
@@ -1606,11 +1603,8 @@
 void list_programmers_linebreak(int startcol, int cols, int paren)
 {
 	const char *pname;
-	int pnamelen;
-	int remaining = 0;
-	int firstline = 1;
+	int pnamelen, remaining = 0, firstline = 1, i;
 	enum programmer p;
-	int i;
 
 	for (p = 0; p < PROGRAMMER_INVALID; p++) {
 		pname = programmer_table[p].name;
@@ -1697,7 +1691,7 @@
 void print_banner(void)
 {
 	msg_ginfo("flashrom is free software, get the source code at "
-		    "http://www.flashrom.org\n");
+		  "http://www.flashrom.org\n");
 	msg_ginfo("\n");
 }
 
@@ -1743,7 +1737,7 @@
 		msg_gerr("Known laptops table does not exist!\n");
 		ret = 1;
 	}
-#endif // CONFIG_INTERNAL == 1
+#endif
 	return ret;
 }
 
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 026e51e..689f276 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -141,13 +141,13 @@
 		const unsigned char *writearr, unsigned char *readarr);
 
 static const struct spi_programmer spi_programmer_ft2232 = {
-	.type = SPI_CONTROLLER_FT2232,
-	.max_data_read = 64 * 1024,
-	.max_data_write = 256,
-	.command = ft2232_spi_send_command,
-	.multicommand = default_spi_send_multicommand,
-	.read = default_spi_read,
-	.write_256 = default_spi_write_256,
+	.type		= SPI_CONTROLLER_FT2232,
+	.max_data_read	= 64 * 1024,
+	.max_data_write	= 256,
+	.command	= ft2232_spi_send_command,
+	.multicommand	= default_spi_send_multicommand,
+	.read		= default_spi_read,
+	.write_256	= default_spi_write_256,
 };
 
 /* Returns 0 upon success, a negative number upon errors. */
@@ -246,21 +246,17 @@
 				ftdic->error_str);
 	}
 
-	if (ftdi_usb_reset(ftdic) < 0) {
+	if (ftdi_usb_reset(ftdic) < 0)
 		msg_perr("Unable to reset FTDI device\n");
-	}
 
-	if (ftdi_set_latency_timer(ftdic, 2) < 0) {
+	if (ftdi_set_latency_timer(ftdic, 2) < 0)
 		msg_perr("Unable to set latency timer\n");
-	}
 
-	if (ftdi_write_data_set_chunksize(ftdic, 256)) {
+	if (ftdi_write_data_set_chunksize(ftdic, 256))
 		msg_perr("Unable to set chunk size\n");
-	}
 
-	if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) {
+	if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0)
 		msg_perr("Unable to set bitmode to SPI\n");
-	}
 
 	if (clock_5x) {
 		msg_pdbg("Disable divide-by-5 front stage\n");
@@ -285,8 +281,7 @@
 	}
 
 	msg_pdbg("MPSSE clock: %f MHz divisor: %d "
-		 "SPI clock: %f MHz\n",
-		 mpsse_clk, DIVIDE_BY,
+		 "SPI clock: %f MHz\n", mpsse_clk, DIVIDE_BY,
 		 (double)(mpsse_clk / (((DIVIDE_BY - 1) + 1) * 2)));
 
 	/* Disconnect TDI/DO to TDO/DI for loopback. */
@@ -328,8 +323,7 @@
 	struct ftdi_context *ftdic = &ftdic_context;
 	static unsigned char *buf = NULL;
 	/* failed is special. We use bitwise ops, but it is essentially bool. */
-	int i = 0, ret = 0, failed = 0;
-	int bufsize;
+	int i = 0, ret = 0, failed = 0, bufsize;
 	static int oldbufsize = 0;
 
 	if (writecnt > 65536 || readcnt > 65536)
@@ -379,8 +373,7 @@
 		failed = ret;
 		/* We can't abort here, we still have to deassert CS#. */
 		if (ret)
-			msg_perr("send_buf failed before read: %i\n",
-				ret);
+			msg_perr("send_buf failed before read: %i\n", ret);
 		i = 0;
 		if (ret == 0) {
 			/*
diff --git a/gfxnvidia.c b/gfxnvidia.c
index 5bf4d4e..4ebf7ee 100644
--- a/gfxnvidia.c
+++ b/gfxnvidia.c
@@ -85,7 +85,7 @@
 
 	nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
 
-	/* must be done before rpci calls */
+	/* Must be done before rpci calls. */
 	if (register_shutdown(gfxnvidia_shutdown, NULL))
 		return 1;
 
diff --git a/hwaccess.h b/hwaccess.h
index a58194f..eea3652 100644
--- a/hwaccess.h
+++ b/hwaccess.h
@@ -220,7 +220,7 @@
   #define INW  inportw
   #define INL  inportl
 
-#else 
+#else
 
   #define OUTB outb
   #define OUTW outw
diff --git a/ichspi.c b/ichspi.c
index 833c0c3..557d5e6 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -362,7 +362,7 @@
 {
 	int a;
 
-	for (a = 0; a < sizeof(POSSIBLE_OPCODES)/sizeof(POSSIBLE_OPCODES[0]); a++) {
+	for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
 		if (POSSIBLE_OPCODES[a].opcode == opcode)
 			return POSSIBLE_OPCODES[a].spi_type;
 	}
diff --git a/it85spi.c b/it85spi.c
index 0107c9b..f56d7bd 100644
--- a/it85spi.c
+++ b/it85spi.c
@@ -90,14 +90,10 @@
  * Returns: 0 -- the expected value has shown.
  *          1 -- timeout reached.
  */
-static int wait_for(
-		const unsigned int mask,
-		const unsigned int expected_value,
-		const int timeout,  /* in usec */
-		const char* error_message,
-		const char* function_name,
-		const int lineno
-) {
+static int wait_for(const unsigned int mask, const unsigned int expected_value,
+		const int timeout /* in usec */, const char *error_message,
+		const char *function_name, const int lineno)
+{
 	int time_passed;
 
 	for (time_passed = 0;; ++time_passed) {
@@ -112,24 +108,23 @@
 	return 1;
 }
 
-/* IT8502 employs a scratch ram when flash is being updated. Call the following
+/* IT8502 employs a scratch RAM when flash is being updated. Call the following
  * two functions before/after flash erase/program. */
-void it85xx_enter_scratch_rom()
+void it85xx_enter_scratch_rom(void)
 {
-	int ret;
-	int tries;
+	int ret, tries;
 
 	msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__);
-	if (it85xx_scratch_rom_reenter > 0) return;
+	if (it85xx_scratch_rom_reenter > 0)
+		return;
 
 #if 0
 	/* FIXME: this a workaround for the bug that SMBus signal would
 	 *        interfere the EC firmware update. Should be removed if
 	 *        we find out the root cause. */
 	ret = system("stop powerd >&2");
-	if (ret) {
+	if (ret)
 		msg_perr("Cannot stop powerd.\n");
-	}
 #endif
 
 	for (tries = 0; tries < MAX_TRY; ++tries) {
@@ -173,7 +168,7 @@
 	}
 }
 
-void it85xx_exit_scratch_rom()
+void it85xx_exit_scratch_rom(void)
 {
 #if 0
 	int ret;
@@ -181,7 +176,8 @@
 	int tries;
 
 	msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__);
-	if (it85xx_scratch_rom_reenter <= 0) return;
+	if (it85xx_scratch_rom_reenter <= 0)
+		return;
 
 	for (tries = 0; tries < MAX_TRY; ++tries) {
 		/* Wait until IBF (input buffer) is not full. */
@@ -220,9 +216,8 @@
 	 *        interfere the EC firmware update. Should be removed if
 	 *        we find out the root cause. */
 	ret = system("start powerd >&2");
-	if (ret) {
+	if (ret)
 		msg_perr("Cannot start powerd again.\n");
-	}
 #endif
 }
 
@@ -245,7 +240,7 @@
 		return 1;
 
 #ifdef LPC_IO
-	/* Get LPCPNP of SHM. That's big-endian */
+	/* Get LPCPNP of SHM. That's big-endian. */
 	sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
 	shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
 	              sio_read(s.port, SHM_IO_BAR1);
@@ -255,8 +250,8 @@
 	/* These pointers are not used directly. They will be send to EC's
 	 * register for indirect access. */
 	base = 0xFFFFF000;
-	ce_high = ((unsigned char*)base) + 0xE00;  /* 0xFFFFFE00 */
-	ce_low = ((unsigned char*)base) + 0xD00;  /* 0xFFFFFD00 */
+	ce_high = ((unsigned char *)base) + 0xE00;  /* 0xFFFFFE00 */
+	ce_low = ((unsigned char *)base) + 0xD00;  /* 0xFFFFFD00 */
 
 	/* pre-set indirect-access registers since in most of cases they are
 	 * 0xFFFFxx00. */
@@ -269,8 +264,8 @@
 						     0xFFFFF000, 0x1000);
 	msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
 	         (unsigned int)base);
-	ce_high = (unsigned char*)(base + 0xE00);  /* 0xFFFFFE00 */
-	ce_low = (unsigned char*)(base + 0xD00);  /* 0xFFFFFD00 */
+	ce_high = (unsigned char *)(base + 0xE00);  /* 0xFFFFFE00 */
+	ce_low = (unsigned char *)(base + 0xD00);  /* 0xFFFFFD00 */
 #endif
 
 	return 0;
@@ -280,13 +275,13 @@
 			const unsigned char *writearr, unsigned char *readarr);
 
 static const struct spi_programmer spi_programmer_it85xx = {
-	.type = SPI_CONTROLLER_IT85XX,
-	.max_data_read = 64,
-	.max_data_write = 64,
-	.command = it85xx_spi_send_command,
-	.multicommand = default_spi_send_multicommand,
-	.read = default_spi_read,
-	.write_256 = default_spi_write_256,
+	.type		= SPI_CONTROLLER_IT85XX,
+	.max_data_read	= 64,
+	.max_data_write	= 64,
+	.command	= it85xx_spi_send_command,
+	.multicommand	= default_spi_send_multicommand,
+	.read		= default_spi_read,
+	.write_256	= default_spi_write_256,
 };
 
 int it85xx_spi_init(struct superio s)
@@ -305,7 +300,7 @@
 		if (buses_supported & BUS_FWH)
 			msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
 		/* Really leave FWH enabled? */
-		/* Set this as spi controller. */
+		/* Set this as SPI controller. */
 		register_spi_programmer(&spi_programmer_it85xx);
 	}
 	return ret;
@@ -324,7 +319,7 @@
 	int i;
 
 	it85xx_enter_scratch_rom();
-	/* exit scratch rom ONLY when programmer shuts down. Otherwise, the
+	/* exit scratch ROM ONLY when programmer shuts down. Otherwise, the
 	 * temporary flash state may halt EC. */
 
 #ifdef LPC_IO
diff --git a/it87spi.c b/it87spi.c
index 9ed71dc..c24ba9b 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -93,8 +93,7 @@
 		case 0x85:
 			msg_pdbg("Found ITE EC, ID 0x%04hx,"
 			         "Rev 0x%02x on port 0x%x.\n",
-			         s.model,
-			         sio_read(s.port, CHIP_VER_REG),
+			         s.model, sio_read(s.port, CHIP_VER_REG),
 			         s.port);
 			register_superio(s);
 			break;
@@ -106,17 +105,19 @@
 
 static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
 			const unsigned char *writearr, unsigned char *readarr);
-static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len);
-static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
+static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf,
+				 int start, int len);
+static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf,
+				      int start, int len);
 
 static const struct spi_programmer spi_programmer_it87xx = {
-	.type = SPI_CONTROLLER_IT87XX,
-	.max_data_read = MAX_DATA_UNSPECIFIED,
-	.max_data_write = MAX_DATA_UNSPECIFIED,
-	.command = it8716f_spi_send_command,
-	.multicommand = default_spi_send_multicommand,
-	.read = it8716f_spi_chip_read,
-	.write_256 = it8716f_spi_chip_write_256,
+	.type		= SPI_CONTROLLER_IT87XX,
+	.max_data_read	= MAX_DATA_UNSPECIFIED,
+	.max_data_write	= MAX_DATA_UNSPECIFIED,
+	.command	= it8716f_spi_send_command,
+	.multicommand	= default_spi_send_multicommand,
+	.read		= it8716f_spi_chip_read,
+	.write_256	= it8716f_spi_chip_write_256,
 };
 
 static uint16_t it87spi_probe(uint16_t port)
@@ -202,8 +203,7 @@
 
 int init_superio_ite(void)
 {
-	int i;
-	int ret = 0;
+	int i, ret = 0;
 
 	for (i = 0; i < superio_count; i++) {
 		if (superios[i].vendor != SUPERIO_VENDOR_ITE)
@@ -259,7 +259,7 @@
 	} while (busy);
 	if (readcnt > 3) {
 		msg_pinfo("%s called with unsupported readcnt %i.\n",
-		       __func__, readcnt);
+			  __func__, readcnt);
 		return SPI_INVALID_LENGTH;
 	}
 	switch (writecnt) {
@@ -289,7 +289,7 @@
 		break;
 	default:
 		msg_pinfo("%s called with unsupported writecnt %i.\n",
-		       __func__, writecnt);
+			  __func__, writecnt);
 		return SPI_INVALID_LENGTH;
 	}
 	/*
@@ -313,10 +313,10 @@
 }
 
 /* Page size is usually 256 bytes */
-static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int start)
+static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf,
+				    int start)
 {
-	int i;
-	int result;
+	int i, result;
 	chipaddr bios = flash->virtual_memory;
 
 	result = spi_write_enable();
@@ -325,9 +325,8 @@
 	/* FIXME: The command below seems to be redundant or wrong. */
 	OUTB(0x06, it8716f_flashport + 1);
 	OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
-	for (i = 0; i < flash->page_size; i++) {
+	for (i = 0; i < flash->page_size; i++)
 		chip_writeb(buf[i], bios + start + i);
-	}
 	OUTB(0, it8716f_flashport);
 	/* Wait until the Write-In-Progress bit is cleared.
 	 * This usually takes 1-10 ms, so wait in 1 ms steps.
@@ -341,7 +340,8 @@
  * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
  * Need to read this big flash using firmware cycles 3 byte at a time.
  */
-static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf,
+				 int start, int len)
 {
 	fast_spi = 0;
 
@@ -358,7 +358,8 @@
 	return 0;
 }
 
-static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf,
+				      int start, int len)
 {
 	/*
 	 * IT8716F only allows maximum of 512 kb SPI chip size for memory
diff --git a/pcidev.c b/pcidev.c
index d4ad8bc..e8b4dc1 100644
--- a/pcidev.c
+++ b/pcidev.c
@@ -247,9 +247,9 @@
 	msg_pinfo("PCI devices:\n");
 	for (i = 0; devs[i].vendor_name != NULL; i++) {
 		msg_pinfo("%s %s [%04x:%04x]%s\n", devs[i].vendor_name,
-		       devs[i].device_name, devs[i].vendor_id,
-		       devs[i].device_id,
-		       (devs[i].status == NT) ? " (untested)" : "");
+		          devs[i].device_name, devs[i].vendor_id,
+		          devs[i].device_id,
+		          (devs[i].status == NT) ? " (untested)" : "");
 	}
 }
 
diff --git a/physmap.c b/physmap.c
index cb035a5..cbab636 100644
--- a/physmap.c
+++ b/physmap.c
@@ -43,16 +43,13 @@
 
 static void *map_first_meg(unsigned long phys_addr, size_t len)
 {
-
-	if (realmem_map) {
+	if (realmem_map)
 		return realmem_map + phys_addr;
-	}
 
 	realmem_map = valloc(1024 * 1024);
 
-	if (!realmem_map) {
+	if (!realmem_map)
 		return ERROR_PTR;
-	}
 
 	if (__djgpp_map_physical_memory(realmem_map, (1024 * 1024), 0)) {
 		free(realmem_map);
@@ -68,23 +65,21 @@
 	int ret;
 	__dpmi_meminfo mi;
 
-	/* enable 4GB limit on DS descriptor */
-	if (!__djgpp_nearptr_enable()) {
+	/* Enable 4GB limit on DS descriptor. */
+	if (!__djgpp_nearptr_enable())
 		return ERROR_PTR;
-	}
 
 	if ((phys_addr + len - 1) < (1024 * 1024)) {
-	/* we need to use another method to map first 1MB */
+		/* We need to use another method to map first 1MB. */
 		return map_first_meg(phys_addr, len);
 	}
 
 	mi.address = phys_addr;
 	mi.size = len;
-	ret =  __dpmi_physical_address_mapping (&mi);
+	ret = __dpmi_physical_address_mapping (&mi);
 
-	if (ret != 0) {
+	if (ret != 0)
 		return ERROR_PTR;
-	}
 
 	return (void *) mi.address + __djgpp_conventional_base;
 }
@@ -99,7 +94,8 @@
 	/* There is no known way to unmap the first 1 MB. The DPMI server will
 	 * do this for us on exit.
 	 */
-	if ((virt_addr >= realmem_map) && ((virt_addr + len) <= (realmem_map + (1024 * 1024)))) {
+	if ((virt_addr >= realmem_map) &&
+	    ((virt_addr + len) <= (realmem_map + (1024 * 1024)))) {
 		return;
 	}
 
@@ -114,7 +110,7 @@
 
 void *sys_physmap(unsigned long phys_addr, size_t len)
 {
-	return (void*)phys_to_virt(phys_addr);
+	return (void *)phys_to_virt(phys_addr);
 }
 
 #define sys_physmap_rw_uncached	sys_physmap
@@ -195,7 +191,8 @@
 	if (-1 == fd_mem_cached) {
 		/* Open the memory device CACHED. */
 		if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) {
-			msg_perr("Critical error: open(" MEM_DEV "): %s", strerror(errno));
+			msg_perr("Critical error: open(" MEM_DEV "): %s",
+				 strerror(errno));
 			exit(2);
 		}
 	}
@@ -221,36 +218,37 @@
 #define PHYSMAP_RW	0
 #define PHYSMAP_RO	1
 
-static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly)
+static void *physmap_common(const char *descr, unsigned long phys_addr,
+			    size_t len, int mayfail, int readonly)
 {
 	void *virt_addr;
 
 	if (len == 0) {
 		msg_pspew("Not mapping %s, zero size at 0x%08lx.\n",
-			     descr, phys_addr);
+			  descr, phys_addr);
 		return ERROR_PTR;
 	}
-		
+
 	if ((getpagesize() - 1) & len) {
 		msg_perr("Mapping %s at 0x%08lx, unaligned size 0x%lx.\n",
-			descr, phys_addr, (unsigned long)len);
+			 descr, phys_addr, (unsigned long)len);
 	}
 
 	if ((getpagesize() - 1) & phys_addr) {
 		msg_perr("Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n",
-			descr, (unsigned long)len, phys_addr);
+			 descr, (unsigned long)len, phys_addr);
 	}
 
-	if (readonly) {
+	if (readonly)
 		virt_addr = sys_physmap_ro_cached(phys_addr, len);
-	} else {
+	else
 		virt_addr = sys_physmap_rw_uncached(phys_addr, len);
-	}
 
 	if (ERROR_PTR == virt_addr) {
 		if (NULL == descr)
 			descr = "memory";
-		msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr);
+		msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr,
+			 (unsigned long)len, phys_addr);
 		perror(MEM_DEV " mmap failed");
 #ifdef __linux__
 		if (EINVAL == errno) {
@@ -262,8 +260,8 @@
 		}
 #elif defined (__OpenBSD__)
 		msg_perr("Please set securelevel=-1 in /etc/rc.securelevel "
-			   "and reboot, or reboot into \n");
-		msg_perr("single user mode.\n");
+			 "and reboot, or reboot into\n"
+			 "single user mode.\n");
 #endif
 		if (!mayfail)
 			exit(3);
@@ -274,12 +272,14 @@
 
 void *physmap(const char *descr, unsigned long phys_addr, size_t len)
 {
-	return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW);
+	return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL,
+			      PHYSMAP_RW);
 }
 
 void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len)
 {
-	return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
+	return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL,
+			      PHYSMAP_RO);
 }
 
 #if defined(__i386__) || defined(__x86_64__)
@@ -288,7 +288,7 @@
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
  * which are ring0 privileged instructions so only the kernel can do the
- * read/write.  This function, therefore, requires that the msr kernel module
+ * read/write. This function, therefore, requires that the msr kernel module
  * be loaded to access these instructions from user space using device
  * /dev/cpu/0/msr.
  */
@@ -309,7 +309,6 @@
 	if (read(fd_msr, buf, 8) == 8) {
 		msr.lo = buf[0];
 		msr.hi = buf[1];
-
 		return msr;
 	}
 
@@ -341,7 +340,7 @@
 		exit(1);
 	}
 
-	/* some MSRs must not be written */
+	/* Some MSRs must not be written. */
 	if (errno == EIO)
 		return -1;
 
@@ -379,7 +378,7 @@
 
 	close(fd_msr);
 
-	/* Clear MSR file descriptor */
+	/* Clear MSR file descriptor. */
 	fd_msr = -1;
 }
 #else
@@ -462,7 +461,7 @@
 
 	close(fd_msr);
 
-	/* Clear MSR file descriptor */
+	/* Clear MSR file descriptor. */
 	fd_msr = -1;
 }