)]}'
{
  "commit": "89569d60e3aeeec651496b2e7a2e6064d782ab3b",
  "tree": "bf0c3951886de60086d32ff6e1a850adad926da6",
  "parents": [
    "929d2e1b17a448d3352dbecb6a620ee0c1e65a58"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Thu Jan 12 23:31:40 2023 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sat Mar 09 10:30:24 2024 +0000"
  },
  "message": "memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`\n\nWe used to store the maximum decode size, i.e. the maximum memory-mapped\nrange of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There\nwas no programmer in the tree that really made use of it, though:\n* The chipset drivers usually focus on a single bus type. And even if\n  they advertise the whole default set (PAR, LPC, FWH), they only pro-\n  vide a maximum decode size for one of them. The latter is probably\n  wrong, should really more than one bus type be supported.\n* PCI and external programmers all support only a single bus type, with\n  the exception of `serprog` which doesn\u0027t set a maximum decode size.\n\nWhat made the distinction even less useful is that for some chips that\nsupport multiple bus types, i.e. LPC+FWH, we can\u0027t even detect which\ntype it is. The existing code around this also only tried to provide\nthe best possible warning message at the expense of breaking the pro-\ngrammer abstraction.\n\nHence, unify the set of sizes into a single `max_rom_decode` property.\nWe store it inside the `registered_master` struct right away, to avoid\nany more use of globals.\n\nChange-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531\n",
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