memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`
We used to store the maximum decode size, i.e. the maximum memory-mapped
range of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There
was no programmer in the tree that really made use of it, though:
* The chipset drivers usually focus on a single bus type. And even if
they advertise the whole default set (PAR, LPC, FWH), they only pro-
vide a maximum decode size for one of them. The latter is probably
wrong, should really more than one bus type be supported.
* PCI and external programmers all support only a single bus type, with
the exception of `serprog` which doesn't set a maximum decode size.
What made the distinction even less useful is that for some chips that
support multiple bus types, i.e. LPC+FWH, we can't even detect which
type it is. The existing code around this also only tried to provide
the best possible warning message at the expense of breaking the pro-
grammer abstraction.
Hence, unify the set of sizes into a single `max_rom_decode` property.
We store it inside the `registered_master` struct right away, to avoid
any more use of globals.
Change-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531
diff --git a/nicintel.c b/nicintel.c
index 1c63081..573b361 100644
--- a/nicintel.c
+++ b/nicintel.c
@@ -93,8 +93,7 @@
*/
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
- max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
- return register_par_master(&par_master_nicintel, BUS_PARALLEL, NULL);
+ return register_par_master(&par_master_nicintel, BUS_PARALLEL, NICINTEL_MEMMAP_SIZE, NULL);
}
static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,