memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`

We used to store the maximum decode size, i.e. the maximum memory-mapped
range of the flash chip, per bus type (Parallel, LPC, FWH, SPI). There
was no programmer in the tree that really made use of it, though:
* The chipset drivers usually focus on a single bus type. And even if
  they advertise the whole default set (PAR, LPC, FWH), they only pro-
  vide a maximum decode size for one of them. The latter is probably
  wrong, should really more than one bus type be supported.
* PCI and external programmers all support only a single bus type, with
  the exception of `serprog` which doesn't set a maximum decode size.

What made the distinction even less useful is that for some chips that
support multiple bus types, i.e. LPC+FWH, we can't even detect which
type it is. The existing code around this also only tried to provide
the best possible warning message at the expense of breaking the pro-
grammer abstraction.

Hence, unify the set of sizes into a single `max_rom_decode` property.
We store it inside the `registered_master` struct right away, to avoid
any more use of globals.

Change-Id: I2aaea18d5b4255eb843a625b016ee74bb145ed85
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/72531
diff --git a/atapromise.c b/atapromise.c
index dcdf4c2..62c7e3d 100644
--- a/atapromise.c
+++ b/atapromise.c
@@ -141,14 +141,12 @@
 		return 1;
 	}
 
-	max_rom_decode.parallel = rom_size;
-
 	msg_pwarn("Do not use this device as a generic programmer. It will leave anything outside\n"
 		  "the first %zu kB of the flash chip in an undefined state. It works fine for the\n"
 		  "purpose of updating the firmware of this device (padding may necessary).\n",
 		  rom_size / 1024);
 
-	return register_par_master(&par_master_atapromise, BUS_PARALLEL, NULL);
+	return register_par_master(&par_master_atapromise, BUS_PARALLEL, rom_size, NULL);
 }
 
 static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)