)]}'
{
  "commit": "880e867ae823dbbd140731f2eaa2ea656b4b9153",
  "tree": "6f6ccde262a1878c3e3fe788e4923811a26628ef",
  "parents": [
    "4b177369854b0f1b0f5769b809f2cf1b0ea4f347"
  ],
  "author": {
    "name": "Michael Karcher",
    "email": "flashrom@mkarcher.dialup.fu-berlin.de",
    "time": "Fri Apr 15 00:03:37 2011 +0000"
  },
  "committer": {
    "name": "Michael Karcher",
    "email": "flashrom@mkarcher.dialup.fu-berlin.de",
    "time": "Fri Apr 15 00:03:37 2011 +0000"
  },
  "message": "Remove delays in JEDEC erase sequence\n\nIt is extremely unlikely that a chip not requiring delays in probe does\nrequire them in erase. We observed unreliable erasing with a SST49LF004A\nwith these delays, so remove them if the are not required.\n\nIn review, I got the hint that \"probe_jedec goes further by making that\ncall conditional on nonzero delay\". I decided to ignore that. For\ninternal_delay, the small amount of clock cycles wasted for calling\nprogrammer_delay(0) is negligible compared to LPC cycle times. It might\nbe an issue for 5 wasted bytes on the serial line in serprog. OTOH,\nflash erase is still slow compared to 6*5 bytes on a serial port at\nreasonable speed.\n\nCorresponding to flashrom svn r1288.\n\nSigned-off-by: Michael Karcher \u003cflashrom@mkarcher.dialup.fu-berlin.de\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "199c64d3e9da00a8ba994c1db00bd1ff7bd0ebe0",
      "old_mode": 33188,
      "old_path": "jedec.c",
      "new_id": "f23cf5352c5fe7605a5a75e6fb91981df28f5b42",
      "new_mode": 33188,
      "new_path": "jedec.c"
    }
  ]
}