ich_descriptors: Hard code number of masters for newer gens
The number of masters (NM) field is ignored by the hardware and often
not updated in Intel's tooling. Since PCH100 / Skylake, it's always
been 2 masters for the small core, 5 for the big core, and 6 for the
server platforms.
Change-Id: I4975f5b55981791fa5b10c4731af8f330cbbefa8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/ich_descriptors.c b/ich_descriptors.c
index f24d353..dfc1cb8 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -71,13 +71,14 @@
{
switch (cs) {
case CHIPSET_C620_SERIES_LEWISBURG:
+ return 6;
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
- if (cont->NM <= MAX_NUM_MASTERS)
- return cont->NM;
- break;
+ return 2;
default:
+ if (cs >= SPI_ENGINE_PCH100)
+ return 5;
if (cont->NM < MAX_NUM_MASTERS)
return cont->NM + 1;
}