flashchips: Add Fudan FM25Q64, update FM25Q08..Q32
For all bits that matter to us, these chips seem to have the same
status-register layout. The FM25Q64 differs in a few bits that are
out-of-scope, and additionally supports a WRSR2.
Datasheets used:
http://eng.fmsh.com/nvm/FM25Q08_ds_eng.pdf
http://eng.fmsh.com/nvm/FM25Q16_ds_eng.pdf
http://eng.fmsh.com/nvm/FM25Q32_ds_eng.pdf
http://eng.fmsh.com/nvm/FM25Q64_ds_eng.pdf
Change-Id: I820ed60366d19ab4d87f8c02b4018ffb5591ca5f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/288
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/flashchips.c b/flashchips.c
index af4c9fd..a5a7a9c 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6718,7 +6718,7 @@
.page_size = 256,
/* supports SFDP */
/* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT2 |
+ .feature_bits = FEATURE_WRSR_EITHER | FEATURE_WRSR_EXT2 |
FEATURE_OTP | FEATURE_QPI_SRP,
.dummy_cycles = { .qpi_read_params = { 2, 4, 6, 8 } },
.tested = TEST_UNTESTED,
@@ -6745,7 +6745,17 @@
.reg_bits =
{
.qe = {STATUS2, 1, RW},
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW},
+ .sec = {STATUS1, 6, RW},
+ .cmp = {STATUS2, 6, RW},
},
+ .wp_write_cfg = spi_wp_write_cfg,
+ .wp_read_cfg = spi_wp_read_cfg,
+ .wp_get_ranges = spi_wp_get_available_ranges,
+ .decode_range = decode_range_spi25,
.printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */
.unlock = spi_disable_blockprotect_bp2_srwd,
.write = spi_chip_write_256,
@@ -6765,7 +6775,7 @@
.page_size = 256,
/* supports SFDP */
/* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT2 |
+ .feature_bits = FEATURE_WRSR_EITHER | FEATURE_WRSR_EXT2 |
FEATURE_OTP | FEATURE_QPI_SRP,
.dummy_cycles = { .qpi_read_params = { 2, 4, 6, 8 } },
.tested = TEST_UNTESTED,
@@ -6792,7 +6802,17 @@
.reg_bits =
{
.qe = {STATUS2, 1, RW},
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW},
+ .sec = {STATUS1, 6, RW},
+ .cmp = {STATUS2, 6, RW},
},
+ .wp_write_cfg = spi_wp_write_cfg,
+ .wp_read_cfg = spi_wp_read_cfg,
+ .wp_get_ranges = spi_wp_get_available_ranges,
+ .decode_range = decode_range_spi25,
.printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */
.unlock = spi_disable_blockprotect_bp2_srwd,
.write = spi_chip_write_256,
@@ -6812,7 +6832,7 @@
.page_size = 256,
/* supports SFDP */
/* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT2 |
+ .feature_bits = FEATURE_WRSR_EITHER | FEATURE_WRSR_EXT2 |
FEATURE_OTP | FEATURE_QPI_SRP,
.dummy_cycles = { .qpi_read_params = { 2, 4, 6, 8 } },
.tested = TEST_UNTESTED,
@@ -6839,7 +6859,73 @@
.reg_bits =
{
.qe = {STATUS2, 1, RW},
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW},
+ .sec = {STATUS1, 6, RW},
+ .cmp = {STATUS2, 6, RW},
},
+ .wp_write_cfg = spi_wp_write_cfg,
+ .wp_read_cfg = spi_wp_read_cfg,
+ .wp_get_ranges = spi_wp_get_available_ranges,
+ .decode_range = decode_range_spi25,
+ .printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */
+ .unlock = spi_disable_blockprotect_bp2_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ .voltage = {2700, 3600},
+ .prepare_access = spi_prepare_io,
+ .finish_access = spi_finish_io,
+ },
+
+ {
+ .vendor = "Fudan",
+ .name = "FM25Q64",
+ .bustype = BUS_SPI,
+ .manufacture_id = FUDAN_ID_NOPREFIX,
+ .model_id = FUDAN_FM25Q64,
+ .total_size = 8192,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_EITHER | FEATURE_WRSR_EXT2 | FEATURE_WRSR2 |
+ FEATURE_OTP | FEATURE_QPI_SRP,
+ .dummy_cycles = { .qpi_read_params = { 2, 4, 6, 8 } },
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 2048} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 256} },
+ .block_erase = spi_block_erase_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 128} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {8192 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { {8192 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ },
+ },
+ .reg_bits =
+ {
+ .qe = {STATUS2, 1, RW},
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW},
+ .sec = {STATUS1, 6, RW},
+ .cmp = {STATUS2, 6, RW},
+ },
+ .wp_write_cfg = spi_wp_write_cfg,
+ .wp_read_cfg = spi_wp_read_cfg,
+ .wp_get_ranges = spi_wp_get_available_ranges,
+ .decode_range = decode_range_spi25,
.printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */
.unlock = spi_disable_blockprotect_bp2_srwd,
.write = spi_chip_write_256,
diff --git a/include/flashchips.h b/include/flashchips.h
index 0fa1afe..4718bd2 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -353,6 +353,7 @@
#define FUDAN_FM25Q08 0x4014
#define FUDAN_FM25Q16 0x4015
#define FUDAN_FM25Q32 0x4016
+#define FUDAN_FM25Q64 0x4017
#define FUJITSU_ID 0x04 /* Fujitsu */
#define FUJITSU_MBM29DL400BC 0x0F