)]}'
{
  "commit": "7f30022fb0fb62a484514e50d5b3f15157a5885d",
  "tree": "61376bc0e4b1059bb7776f76df178961a5ae74a9",
  "parents": [
    "14e50ac12310eac97f64ee8d6cb17dfb6407259b"
  ],
  "author": {
    "name": "Jason Wang",
    "email": "Qingpei.Wang@amd.com",
    "time": "Fri Nov 28 05:40:27 2008 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Fri Nov 28 05:40:27 2008 +0000"
  },
  "message": "Add SST25VF080B flash chip support\n\nThis is the first chip which uses the infrastructure for alternative\nerase commands, namely spi_chip_erase_60_c7().\n\nCorresponding to flashrom svn r350 and coreboot v2 svn r3776.\n\nSigned-off-by:  Jason Wang \u003cQingpei.Wang@amd.com\u003e\nReviewed-by:   Joe Bao \u003czheng.bao@amd.com\u003e\nAcked-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e7c57f6ddcf0529b61e890f0ec918cf1e0269c6c",
      "old_mode": 33188,
      "old_path": "flashchips.c",
      "new_id": "d6f399d7150ca4133ae52690d7cba10c1b49ad50",
      "new_mode": 33188,
      "new_path": "flashchips.c"
    }
  ]
}