tree 9981905ba97c0509e8686782855d97cffe77d80e
parent 4cbc1cb32dec2a269a6c2fb8d391f36db174bb32
author Subrata Banik <subratabanik@google.com> 1647443442 +0530
committer Felix Singer <felixsinger@posteo.net> 1667123015 +0000

ichspi: Unify timeouts across all SPI operations to 30s

Note: This patch was backported from the master branch and it was
modified so that it can be applied on the 1.2.x branch.

`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument
in favor of a fixed timeout of `30 seconds` for any given SPI operation
as recommended by the SPI programming guide.

Document: Alder Lake-P Client Platform SPI Programming Guide
          Rev 1.30 (supporting document for multi-master accessing the
                    SPI Flash device.)

Refer to below section to understand the problem in more detail and SPI
operation timeout recommendation from Intel in multi-master
scenarios.

On Intel Chipsets that support multi-mastering access of the SPI flash
may run into a timeout failure when the operation initiated from a
single master just follows the SPI operational timeout recommendation
as per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR
specification, table 9.7).

In the multi-master SPI accessing scenario using hardware sequencing
operation, it's impossible to know the actual status of the SPI bus
prior to individual master starting the operation (SPI Cycle In Progress
a.k.a SCIP bit represents the status of SPI operation on individual
master).

Thus, any SPI operation triggered in multi-master environment might need
to account a worst case scenario where the most time consuming operation
might have occupied the SPI bus from a master and an operation initiated
by another master just timed out.

Here is the timeout calculation for any hardware sequencing operation:
  Worst Case Operational Delay =
        (Maximum Time consumed by a SPI operation + Any marginal
	                 adjustment)

  Timeout Recommendation for Hardware Sequencing Operation =
        ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +
                        Current Operational latency)

Assume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC,
GbE and other reserved etc, hence, the Timeout Calculation for SPI
erase Operation would look like as below:

  Maximum Time consumed by a SPI Operation =  5 seconds

  Worst Case Operational Delay = 5 seconds

  Timeout Recommendation for Hardware Seq Operation =
             5 seconds * (6 - 1) + 5 seconds = 30 seconds

BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).

Original-Signed-off-by: Subrata Banik <subratabanik@google.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>