)]}'
{
  "commit": "7cb43957c5fe405cd82584f0a54428f2d2d286ff",
  "tree": "9981905ba97c0509e8686782855d97cffe77d80e",
  "parents": [
    "4cbc1cb32dec2a269a6c2fb8d391f36db174bb32"
  ],
  "author": {
    "name": "Subrata Banik",
    "email": "subratabanik@google.com",
    "time": "Wed Mar 16 20:40:42 2022 +0530"
  },
  "committer": {
    "name": "Felix Singer",
    "email": "felixsinger@posteo.net",
    "time": "Sun Oct 30 09:43:35 2022 +0000"
  },
  "message": "ichspi: Unify timeouts across all SPI operations to 30s\n\nNote: This patch was backported from the master branch and it was\nmodified so that it can be applied on the 1.2.x branch.\n\n`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument\nin favor of a fixed timeout of `30 seconds` for any given SPI operation\nas recommended by the SPI programming guide.\n\nDocument: Alder Lake-P Client Platform SPI Programming Guide\n          Rev 1.30 (supporting document for multi-master accessing the\n                    SPI Flash device.)\n\nRefer to below section to understand the problem in more detail and SPI\noperation timeout recommendation from Intel in multi-master\nscenarios.\n\nOn Intel Chipsets that support multi-mastering access of the SPI flash\nmay run into a timeout failure when the operation initiated from a\nsingle master just follows the SPI operational timeout recommendation\nas per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR\nspecification, table 9.7).\n\nIn the multi-master SPI accessing scenario using hardware sequencing\noperation, it\u0027s impossible to know the actual status of the SPI bus\nprior to individual master starting the operation (SPI Cycle In Progress\na.k.a SCIP bit represents the status of SPI operation on individual\nmaster).\n\nThus, any SPI operation triggered in multi-master environment might need\nto account a worst case scenario where the most time consuming operation\nmight have occupied the SPI bus from a master and an operation initiated\nby another master just timed out.\n\nHere is the timeout calculation for any hardware sequencing operation:\n  Worst Case Operational Delay \u003d\n        (Maximum Time consumed by a SPI operation + Any marginal\n\t                 adjustment)\n\n  Timeout Recommendation for Hardware Sequencing Operation \u003d\n        ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +\n                        Current Operational latency)\n\nAssume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC,\nGbE and other reserved etc, hence, the Timeout Calculation for SPI\nerase Operation would look like as below:\n\n  Maximum Time consumed by a SPI Operation \u003d  5 seconds\n\n  Worst Case Operational Delay \u003d 5 seconds\n\n  Timeout Recommendation for Hardware Seq Operation \u003d\n             5 seconds * (6 - 1) + 5 seconds \u003d 30 seconds\n\nBUG\u003db:223630977\nTEST\u003dAble to perform read/write/erase operation on PCH 600 series\nchipset (board name: Brya).\n\nOriginal-Signed-off-by: Subrata Banik \u003csubratabanik@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867\nOriginal-Tested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nOriginal-Reviewed-by: Anastasia Klimchuk \u003caklm@chromium.org\u003e\nOriginal-Reviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nChange-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b\nSigned-off-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/68691\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Michael Niewöhner \u003cfoss@mniewoehner.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "12ee126fba1ad1229361445a3ef4158bc16abd8a",
      "old_mode": 33188,
      "old_path": "ichspi.c",
      "new_id": "725bfb3670bd56a6aa3983d49af2e6c702dcdacd",
      "new_mode": 33188,
      "new_path": "ichspi.c"
    }
  ]
}