diff --git a/ichspi.c b/ichspi.c
index d59fd3b..0b00466 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -399,6 +399,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 		break;
 	default:
 		pprint_reg(HSFS, BERASE, reg_val, ", ");
@@ -409,6 +410,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 		pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
 		pprint_reg(HSFS, WRSDIS, reg_val, ", ");
 		break;
@@ -428,6 +430,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 		_pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
 		pprint_reg(HSFC, WET, reg_val, ", ");
 		break;
@@ -1739,6 +1742,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		num_pr			= 6;	/* Includes GPR0 */
@@ -1771,6 +1775,7 @@
 		num_freg = 12;	/* 12 MMIO regs, but 16 regions in FD spec */
 		break;
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		num_freg = 16;
@@ -1867,6 +1872,7 @@
 		case CHIPSET_100_SERIES_SUNRISE_POINT:
 		case CHIPSET_C620_SERIES_LEWISBURG:
 		case CHIPSET_300_SERIES_CANNON_POINT:
+		case CHIPSET_500_SERIES_TIGER_POINT:
 		case CHIPSET_APOLLO_LAKE:
 		case CHIPSET_GEMINI_LAKE:
 			tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
@@ -1942,6 +1948,7 @@
 			case CHIPSET_100_SERIES_SUNRISE_POINT:
 			case CHIPSET_C620_SERIES_LEWISBURG:
 			case CHIPSET_300_SERIES_CANNON_POINT:
+			case CHIPSET_500_SERIES_TIGER_POINT:
 			case CHIPSET_APOLLO_LAKE:
 			case CHIPSET_GEMINI_LAKE:
 			case CHIPSET_BAYTRAIL:
@@ -1975,6 +1982,7 @@
 			case CHIPSET_100_SERIES_SUNRISE_POINT:
 			case CHIPSET_C620_SERIES_LEWISBURG:
 			case CHIPSET_300_SERIES_CANNON_POINT:
+			case CHIPSET_500_SERIES_TIGER_POINT:
 			case CHIPSET_APOLLO_LAKE:
 			case CHIPSET_GEMINI_LAKE:
 				break;
@@ -2007,7 +2015,8 @@
 
 		if (ich_spi_mode == ich_auto &&
 		    (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
-		     ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) {
+		     ich_gen == CHIPSET_300_SERIES_CANNON_POINT ||
+		     ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) {
 			msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
 			ich_spi_mode = ich_hwseq;
 		}