commit 756b6b32e2a49c487d4bbc42d370e8826b41c922
author Nico Huber <nico.h@gmx.de> Wed Dec 21 17:15:13 2022 +0000
committer Nico Huber <nico.h@gmx.de> Thu Jan 05 16:35:01 2023 +0000
tree ce4db0712ab0fba0c5bed684ca67e012a2f2807d
parent 15095dbb7b9d7f1938d43e5ff3b99054b0798803

Add Intel Jasper Lake support

Loosely based on commit b01d7e9f (ichspi: Add Jasper Lake support)
on flashrom master.

Besides a little change in descriptor detection, no difference to
Cannon Point was found. Hence, add new PCI IDs as 300 series.

Change-Id: I9c715c1a5f1ceea32dc51669453d89b315ba8ca2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71453
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

chipset_enable.c

diff --git a/chipset_enable.c b/chipset_enable.c
index 4683da4..182410a 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2120,6 +2120,7 @@
 	{0x8086, 0x068d, B_S,    NT,  "Intel", "HM470",				enable_flash_pch300},
 	{0x8086, 0x068e, B_S,    NT,  "Intel", "WM490",				enable_flash_pch300},
 	{0x8086, 0x0697, B_S,    NT,  "Intel", "W480",				enable_flash_pch300},
+	{0x8086, 0x4da4, B_S,    NT,  "Intel", "Jasper Lake",			enable_flash_pch300},
 	{0x8086, 0x4384, B_S,    NT,  "Intel", "Q570",				enable_flash_pch500},
 	{0x8086, 0x4385, B_S,    NT,  "Intel", "Z590",				enable_flash_pch500},
 	{0x8086, 0x4386, B_S,    NT,  "Intel", "H570",				enable_flash_pch500},

ich_descriptors.c

diff --git a/ich_descriptors.c b/ich_descriptors.c
index fb050c2..bad2b33 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -1028,8 +1028,12 @@
 			return CHIPSET_500_SERIES_TIGER_POINT;
 		if (content->CSSL == 0x14) /* backwards compatible Alder Point */
 			return CHIPSET_500_SERIES_TIGER_POINT;
-		if (content->CSSL == 0x03)
-			return CHIPSET_ELKHART_LAKE;
+		if (content->CSSL == 0x03) {
+			if (content->CSSO == 0x58)
+				return CHIPSET_ELKHART_LAKE;
+			else if (content->CSSO == 0x6c) /* backwards compatible Jasper Lake */
+				return CHIPSET_300_SERIES_CANNON_POINT;
+		}
 		msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
 		return CHIPSET_500_SERIES_TIGER_POINT;
 	}

util/ich_descriptors_tool/ich_descriptors_tool.c

diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index 05208c8..2a6c0d8 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -128,6 +128,7 @@
 "\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n"
 "\t- \"apollo\" for Intel's Apollo Lake SoC.\n"
 "\t- \"gemini\" for Intel's Gemini Lake SoC.\n"
+"\t- \"jasper\" for Intel's Jasper Lake SoC.\n"
 "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n"
 "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n"
 "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n"
@@ -229,7 +230,8 @@
 		else if ((strcmp(csn, "300") == 0) ||
 			 (strcmp(csn, "cannon") == 0) ||
 			 (strcmp(csn, "400") == 0) ||
-			 (strcmp(csn, "comet") == 0))
+			 (strcmp(csn, "comet") == 0) ||
+			 (strcmp(csn, "jasper") == 0))
 			cs = CHIPSET_300_SERIES_CANNON_POINT;
 		else if ((strcmp(csn, "500") == 0) ||
 			 (strcmp(csn, "tiger") == 0) ||