)]}'
{
  "commit": "721a4f390410debb77487562c8a47a20edb4d7f2",
  "tree": "cf842e10410c39de9bf712d547cdd23f40a5a19b",
  "parents": [
    "ef88423928abf61fa894d2798a9d265fd001cd26"
  ],
  "author": {
    "name": "Nikolai Artemiev",
    "email": "nartemiev@google.com",
    "time": "Mon Dec 14 07:39:02 2020 +1100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Dec 30 01:16:37 2022 +0100"
  },
  "message": "spi25_statusreg.c: restore SR contents at flashrom exit\n\nregister_chip_restore() provides a general mechanism for restoring a chip\u0027s state at flashrom exit; it can be used whenever the SR needs to be changed temporarily to perform some operation and changed back after the operation is complete. The only current current use case is in s25f.c, which changes the SR\u0027s sector layout bits so that entire flash accessible.\n\nThis patch uses the chip restore functionality to reset changes to the status register made by spi_disable_blockprotect_generic(). This should help to ensure consistency across multiple runs of flashrom and make it easier to predict how a specific operation will change the flash.\n\nImported from cros flashrom at `b170dd4e1d5c33b169c5`\n\nChange-Id: If2f0e73518d40519b7569f627c90a34c364df47c\nSigned-off-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/48778\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70943\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "34f9ad4e1129fa9783a65e6865df76e8a0f83260",
      "old_mode": 33188,
      "old_path": "spi25_statusreg.c",
      "new_id": "a0b0fcf5e20d26e50b387332f76c49514e6dc9dc",
      "new_mode": 33188,
      "new_path": "spi25_statusreg.c"
    }
  ]
}