)]}'
{
  "commit": "6d72efaff26d50626008f7f52f710cf2e263b5c6",
  "tree": "9feda016aaca2da0b89d55d4c2aab70dbca8f72b",
  "parents": [
    "092a699d02a5003b323ed6df5a9e1b1241c4d620"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sun Aug 25 13:01:23 2024 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sun Nov 10 13:58:05 2024 +0000"
  },
  "message": "chipset_enable: Remove hidden-spidev workaround for all 14nm PCHs\n\nWhen the 300 and 400 series PCH (Cannon Point, Comet Point)  support\nwas added, we did not know if all firmware will be consistent in the\ndecision not to hide the SPI PCI devices.  A few years later, we can\nconfirm that it is: Grepping[1] through the `linuxhw\u0027 database[2] re-\nveals that we actually gain some hardware support, when matching the\nSPI PCI device directly.\n\nH410 and B460 are actually 22nm \"PCH V\", so they keep the workaround.\n\nJasper Lake already used the PCI ID of the SPI device.\n\nTested read/erase/write on CM246 (Cannon Point).\n\n[1] diff -u \u003c(git grep -lE \u00271f.5.*8086:(9da4|02a4|34a4|a324|06a4)\u0027 \\\n              | grep -v README) \\\n            \u003c(git grep -lE \u00271f.0.*8086:(9d84|028[45]|a30[3-68-ac-e]|3482|068[457c-e]|0697)\u0027 \\\n              | grep -v README)\n[2] https://github.com/linuxhw/LsPCI/\n\nChange-Id: I1b490207818d3a44c8037b6d4046eefe6ead7bda\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/252\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f2c9d165f61b1b855a21b049a19fac9cba8c0482",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "e615a1fce6600ea1734786a1d410ca5a8c53902d",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}