ichspi: Add Intel Arrow Lake support
ARL looks much like a desktop version of Meteor Lake. Hardware registers
seem to be the same, and the descriptor mostly differs in strap settings
(as far as we are concerned).
Odd enough, the old (pre 500 series) format for processor straps is used
again. For the descriptor detection, we shuffle the old default for Ibex
Peak around, and make Arrow Lake the default for everything with over 80
PCH traps.
Tested `ich_descriptors_tool' output for a GIGABYTE Z890M GAMING X BIOS.
Documents used:
* Intel® Core™ Ultra 200S Series Processors Datasheet, Volumes 1 and 2
* Arrow Lake-S and Arrow Lake-HX Client Platform
SPI Programming Guide
Change-Id: Ibaaeb896273eed3806561ba8c01d89770d27ff18
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/270
diff --git a/chipset_enable.c b/chipset_enable.c
index bb6b034..8818dcd 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -708,6 +708,7 @@
case CHIPSET_SNOW_RIDGE: /* hard coded to 0 (SPI) */
case CHIPSET_METEOR_LAKE:
case CHIPSET_LUNAR_LAKE:
+ case CHIPSET_ARROW_LAKE:
boot_straps = boot_straps_apl;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -1039,6 +1040,12 @@
return enable_flash_pch_spidev(spi_dev, name, CHIPSET_LUNAR_LAKE);
}
+static int enable_flash_arl(struct flashprog_programmer *const prog,
+ struct pci_dev *const spi_dev, const char *const name)
+{
+ return enable_flash_pch_spidev(spi_dev, name, CHIPSET_ARROW_LAKE);
+}
+
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
*
@@ -2242,6 +2249,7 @@
{0x8086, 0x18e0, ANY_REV, B_S, NT, "Intel", "Snow Ridge", enable_flash_snowridge},
{0x8086, 0x7e23, ANY_REV, B_S, DEP, "Intel", "Meteor Lake", enable_flash_mtl},
{0x8086, 0xa823, ANY_REV, B_S, NT, "Intel", "Lunar Lake", enable_flash_lnl},
+ {0x8086, 0xae23, ANY_REV, B_S, NT, "Intel", "Arrow Lake", enable_flash_arl},
#endif
{0},
};
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 6bcbbed..4b8169f 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -51,6 +51,7 @@
case CHIPSET_SNOW_RIDGE:
case CHIPSET_METEOR_LAKE:
case CHIPSET_LUNAR_LAKE:
+ case CHIPSET_ARROW_LAKE:
return 16;
case CHIPSET_100_SERIES_SUNRISE_POINT:
return 10;
@@ -78,6 +79,7 @@
case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_SNOW_RIDGE:
case CHIPSET_METEOR_LAKE:
+ case CHIPSET_ARROW_LAKE:
return 6;
case CHIPSET_LUNAR_LAKE:
return 7;
@@ -101,6 +103,7 @@
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_C740_SERIES_EMMITSBURG:
+ case CHIPSET_ARROW_LAKE:
return true;
default:
return cs < SPI_ENGINE_PCH100;
@@ -135,6 +138,7 @@
"C620 series Lewisburg", "300/400 series Cannon/Comet Point",
"500/600 series Tiger/Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
"C740 series Emmitsburg", "Snow Ridge", "Meteor Lake", "Lunar Lake",
+ "800 series Arrow Lake",
};
if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
cs = 0;
@@ -315,6 +319,7 @@
case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_METEOR_LAKE:
case CHIPSET_LUNAR_LAKE:
+ case CHIPSET_ARROW_LAKE:
return freq_str[3][value];
case CHIPSET_ELKHART_LAKE:
return freq_str[4][value];
@@ -358,6 +363,7 @@
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_METEOR_LAKE:
case CHIPSET_LUNAR_LAKE:
+ case CHIPSET_ARROW_LAKE:
msg_pdbg2("Read Clock Frequency: %s\n", "reserved");
return;
default:
@@ -1043,6 +1049,10 @@
warn_peculiar_desc("Gemini Lake");
return CHIPSET_GEMINI_LAKE;
}
+ if (content->ISL < 0x50) { /* arbitrary choice, just say < 0x50 is old */
+ warn_peculiar_desc("Ibex Peak");
+ return CHIPSET_5_SERIES_IBEX_PEAK;
+ }
if (content->NM == 6) {
/* 0x8b is from the SPI Guide, but not yet seen in the wild. */
if (0x50 <= content->ISL && content->ISL <= 0x8b)
@@ -1050,8 +1060,10 @@
warn_peculiar_desc("C740 series");
return CHIPSET_C740_SERIES_EMMITSBURG;
}
- warn_peculiar_desc("Ibex Peak");
- return CHIPSET_5_SERIES_IBEX_PEAK;
+ if (content->ISL == 0xb3 && content->MSL == 0x3a)
+ return CHIPSET_ARROW_LAKE;
+ warn_peculiar_desc("Arrow Lake");
+ return CHIPSET_ARROW_LAKE;
} else if (upper->MDTBA == 0x00) {
if (content->ICCRIBA < 0x31 && content->FMSBA < 0x30) {
if (content->MSL == 0 && content->ISL <= 17)
diff --git a/include/programmer.h b/include/programmer.h
index 8f83155..11d15a8 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -370,6 +370,7 @@
CHIPSET_SNOW_RIDGE,
CHIPSET_METEOR_LAKE,
CHIPSET_LUNAR_LAKE,
+ CHIPSET_ARROW_LAKE,
};
/* ichspi.c */
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index e5444de..5cad9d4 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -141,6 +141,7 @@
"\t- \"600\" or \"alder\" for Intel's 600 series chipsets.\n"
"\t- \"meteor\" for Intel's Meteor Lake SoC.\n"
"\t- \"lunar\" for Intel's Lunar Lake SoC.\n"
+"\t- \"800\" or \"arrow\" for Intel's 800 series chipsets.\n"
"\t- \"c620\" or \"lewis\" for Intel's C620 series aka. Lewisburg chipsets.\n"
"\t- \"c740\" or \"emmits\" for Intel's C740 series chipsets.\n"
"\t- \"snow\" for Intel's Snow Ridge SoC.\n"
@@ -247,6 +248,9 @@
cs = CHIPSET_METEOR_LAKE;
else if (strcmp(csn, "lunar") == 0)
cs = CHIPSET_LUNAR_LAKE;
+ else if ((strcmp(csn, "800") == 0) ||
+ (strcmp(csn, "arrow") == 0))
+ cs = CHIPSET_ARROW_LAKE;
else if (strcmp(csn, "apollo") == 0)
cs = CHIPSET_APOLLO_LAKE;
else if (strcmp(csn, "gemini") == 0)