tree 473c877a4c2901830e7a8005aa45b07d50323e9d
parent 045b97ebd97426b70706db7338a7fd76790b8781
author Thomas Heijligen <thomas.heijligen@secunet.com> 1553011203 +0100
committer Nico Huber <nico.h@gmx.de> 1565299764 +0000

chipset_enable: Add support for discrete Cannon Lake PCHs

The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the
Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted.

[1] Intel(R) 300 Series and Intel(R) C240 Series
    Chipset Family Platform Controller Hub
    Datasheet - Volume 1 of 2
    Revison 4 (Dec 2018)
    Document Number 337347

[2] Intel(R) 300 Series Chipset Families Platform Controller Hub
    Datasheet - Volume 2 of 2
    Revision 2? (Oct 2018)
    Document Number 337348

Change-Id: If0b54799d5b93169ee660409bad57ae14677340c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jeremy Soller <jackpot51@gmail.com>