)]}'
{
  "commit": "5ec84b3c096c9ace0bf3650206a0a9412e977c64",
  "tree": "473c877a4c2901830e7a8005aa45b07d50323e9d",
  "parents": [
    "045b97ebd97426b70706db7338a7fd76790b8781"
  ],
  "author": {
    "name": "Thomas Heijligen",
    "email": "thomas.heijligen@secunet.com",
    "time": "Tue Mar 19 17:00:03 2019 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Thu Aug 08 21:29:24 2019 +0000"
  },
  "message": "chipset_enable: Add support for discrete Cannon Lake PCHs\n\nThe Cannon Lake \"300 Series\" PCHs [1,2] share the register layout of the\nSkylake \"100 Series\". Mark them as BAD until `ichspi.c` is adapted.\n\n[1] Intel(R) 300 Series and Intel(R) C240 Series\n    Chipset Family Platform Controller Hub\n    Datasheet - Volume 1 of 2\n    Revison 4 (Dec 2018)\n    Document Number 337347\n\n[2] Intel(R) 300 Series Chipset Families Platform Controller Hub\n    Datasheet - Volume 2 of 2\n    Revision 2? (Oct 2018)\n    Document Number 337348\n\nChange-Id: If0b54799d5b93169ee660409bad57ae14677340c\nSigned-off-by: Thomas Heijligen \u003cthomas.heijligen@secunet.com\u003e\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/34071\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-by: Matt DeVillier \u003cmatt.devillier@gmail.com\u003e\nReviewed-by: Jeremy Soller \u003cjackpot51@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8c884a892dc531d9a1b983688861500ccb642d44",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "877b8b6462e6dfb4715defb3f253a4ad783b09f0",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    },
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      "old_id": "dfa6ebd018d71ae25097567c72e94392e9148480",
      "old_mode": 33188,
      "old_path": "programmer.h",
      "new_id": "34ef33d502931362f37cbe21a0443ff5d25eafb2",
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      "new_path": "programmer.h"
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}