ichspi: Add Intel Meteor Lake SoC
Hardware looks the same as C740 series / Emmitsburg. The descriptor
is somewhere between the latter and latest desktop platforms.
Output of `ich_descriptors_tool' with an image from Google/Rex looks
reasonable.
Tested probing and reading on a Lenovo L16 ThinkPad.
Documents used:
* Intel® Core™ Ultra Processor Datasheet, Volumes 1 and 2
* Meteor Lake/Arrow Lake-U / H Client Platform
SPI Programming Guide
Change-Id: I7f1d162622a141fadcad715b064f92b1ccf7c72a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/189
diff --git a/chipset_enable.c b/chipset_enable.c
index 5a89589..29032fb 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -706,6 +706,7 @@
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_SNOW_RIDGE: /* hard coded to 0 (SPI) */
+ case CHIPSET_METEOR_LAKE:
boot_straps = boot_straps_apl;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -1025,6 +1026,12 @@
return enable_flash_pch_spidev(spi_dev, name, CHIPSET_SNOW_RIDGE);
}
+static int enable_flash_mtl(struct flashprog_programmer *const prog,
+ struct pci_dev *const spi_dev, const char *const name)
+{
+ return enable_flash_pch_spidev(spi_dev, name, CHIPSET_METEOR_LAKE);
+}
+
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
*
@@ -2226,6 +2233,7 @@
{0x8086, 0x7a24, ANY_REV, B_S, NT, "Intel", "Raptor Lake-S", enable_flash_pch500},
{0x8086, 0x7aa4, ANY_REV, B_S, NT, "Intel", "Alder Lake-S", enable_flash_pch500},
{0x8086, 0x18e0, ANY_REV, B_S, NT, "Intel", "Snow Ridge", enable_flash_snowridge},
+ {0x8086, 0x7e23, ANY_REV, B_S, DEP, "Intel", "Meteor Lake", enable_flash_mtl},
#endif
{0},
};