)]}'
{
  "commit": "5c9f542bf8ce514c628c59e42e35fbcb615d8937",
  "tree": "bcc2215bccd5a34f07460ff0f680aa7fba224744",
  "parents": [
    "cce1e5b8636ebef59dd509680594e17b0a207857"
  ],
  "author": {
    "name": "Michał Żygowski",
    "email": "michal.zygowski@3mdeb.com",
    "time": "Wed Jun 16 15:13:54 2021 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Thu Jan 05 16:15:22 2023 +0000"
  },
  "message": "Add Tiger Lake U Premium support\n\nTiger Lake has very low ICCRIBA (TGL\u003d0x11, CNL\u003d0x34 and CML\u003d0x34) and\ndetects as unknown chipset compatible with 300 series chipset. Add a\nnew enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to\nCHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,\nICCRIBA is no longer present n descriptor content so a new union has\nbeen defined for new fields and used in descriptor guessing.\nfreq_read field is not present on Tiger Lake, moreover in CannonPoint\nand Comet Point this field is used as eSPI/EC frequency, so a new\nfunction to print read frequency has ben added. Finally Tiger lake\nboot straps include eSPI, so a new bus has been added for the new\nstraps.\n\nTested: Flash BIOS region on Intel i5-1135G7\n\nSigned-off-by: Michał Żygowski \u003cmichal.zygowski@3mdeb.com\u003e\nChange-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578\nOriginal-Reviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
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