diff --git a/chipset_enable.c b/chipset_enable.c
index 65cc7c1..a86013c 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -599,6 +599,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		reg_name = "BIOS_SPI_BC";
@@ -652,6 +653,9 @@
 	static const struct boot_straps boot_straps_pch8_lp[] =
 		{ { "SPI", BUS_SPI },
 		  { "LPC", BUS_LPC | BUS_FWH } };
+	static const struct boot_straps boot_straps_pch500[] =
+		{ { "SPI", BUS_SPI },
+		  { "eSPI", BUS_NONE } };
 	static const struct boot_straps boot_straps_apl[] =
 		{ { "SPI", BUS_SPI },
 		  { "reserved", BUS_NONE } };
@@ -697,6 +701,9 @@
 	case CHIPSET_300_SERIES_CANNON_POINT:
 		boot_straps = boot_straps_pch8_lp;
 		break;
+	case CHIPSET_500_SERIES_TIGER_POINT:
+		boot_straps = boot_straps_pch500;
+		break;
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		boot_straps = boot_straps_apl;
@@ -724,6 +731,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		bbs = (gcs >> 6) & 0x1;
@@ -966,6 +974,11 @@
 	return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
 }
 
+static int enable_flash_pch500(struct pci_dev *const dev, const char *const name)
+{
+	return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT);
+}
+
 static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
 {
 	return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
@@ -2021,6 +2034,7 @@
 	{0x8086, 0x9d84, B_S,    DEP, "Intel", "Cannon Lake U Premium",		enable_flash_pch300},
 	{0x8086, 0x0284, B_S,    DEP, "Intel", "Comet Lake U Premium",		enable_flash_pch300},
 	{0x8086, 0x0285, B_S,    DEP, "Intel", "Comet Lake U Base",		enable_flash_pch300},
+	{0x8086, 0xa082, B_S,    DEP, "Intel", "Tiger Lake U Premium",		enable_flash_pch500},
 	{0x8086, 0xa141, B_S,    NT,  "Intel", "Sunrise Point Desktop Sample",	enable_flash_pch100},
 	{0x8086, 0xa142, B_S,    NT,  "Intel", "Sunrise Point Unknown Sample",	enable_flash_pch100},
 	{0x8086, 0xa143, B_S,    DEP, "Intel", "H110",				enable_flash_pch100},
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 63d4580..ac3602b 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -44,6 +44,7 @@
 		return 6;
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 		return 16;
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 		return 10;
@@ -107,7 +108,7 @@
 		"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
 		"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
 		"C620 series Lewisburg", "300/400 series Cannon/Comet Point",
-		"Apollo Lake", "Gemini Lake",
+		"500 series Tiger Point", "Apollo Lake", "Gemini Lake",
 	};
 	if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
 		cs = 0;
@@ -200,6 +201,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE: {
 		uint8_t size_enc;
@@ -220,7 +222,7 @@
 
 static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
 {
-	static const char *const freq_str[3][8] = { {
+	static const char *const freq_str[4][8] = { {
 		"20 MHz",
 		"33 MHz",
 		"reserved",
@@ -247,7 +249,16 @@
 		"reserved",
 		"14 MHz / 17 MHz",
 		"reserved"
-	} };
+	}, {
+		"100 MHz",
+		"50 MHz",
+		"reserved",
+		"33 MHz",
+		"25 MHz",
+		"reserved",
+		"14 MHz",
+		"reserved"
+	}};
 
 	switch (cs) {
 	case CHIPSET_ICH8:
@@ -273,12 +284,40 @@
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		return freq_str[2][value];
+	case CHIPSET_500_SERIES_TIGER_POINT:
+		return freq_str[3][value];
 	case CHIPSET_ICH_UNKNOWN:
 	default:
 		return "unknown";
 	}
 }
 
+static void pprint_read_freq(enum ich_chipset cs, uint8_t value)
+{
+	static const char *const freq_str[1][8] = { {
+		"20 MHz",
+		"24 MHz",
+		"30 MHz",
+		"48 MHz",
+		"60 MHz",
+		"reserved",
+		"reserved",
+		"reserved"
+	}};
+
+	switch (cs) {
+	case CHIPSET_300_SERIES_CANNON_POINT:
+		msg_pdbg2("eSPI/EC Bus Clock Frequency:    %s\n", freq_str[0][value]);
+		return;
+	case CHIPSET_500_SERIES_TIGER_POINT:
+		msg_pdbg2("Read Clock Frequency:           %s\n", "reserved");
+		return;
+	default:
+		msg_pdbg2("Read Clock Frequency:           %s\n", pprint_freq(cs, value));
+		return;
+	}
+}
+
 void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc)
 {
 	bool has_flill1;
@@ -287,6 +326,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		has_flill1 = true;
@@ -309,7 +349,9 @@
 		msg_pdbg2("Component 2 density:            %s\n", pprint_density(cs, desc, 1));
 	else
 		msg_pdbg2("Component 2 is not used.\n");
-	msg_pdbg2("Read Clock Frequency:           %s\n", pprint_freq(cs, desc->component.modes.freq_read));
+
+	pprint_read_freq(cs, desc->component.modes.freq_read);
+
 	msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_read_id));
 	msg_pdbg2("Write and Erase Clock Freq.:    %s\n", pprint_freq(cs, desc->component.modes.freq_write));
 	msg_pdbg2("Fast Read is %ssupported.\n", desc->component.modes.fastread ? "" : "not ");
@@ -406,7 +448,8 @@
 
 	msg_pdbg2("--- Details ---\n");
 	if (cs == CHIPSET_100_SERIES_SUNRISE_POINT ||
-	    cs == CHIPSET_300_SERIES_CANNON_POINT) {
+	    cs == CHIPSET_300_SERIES_CANNON_POINT ||
+	    cs == CHIPSET_500_SERIES_TIGER_POINT) {
 		const char *const master_names[] = {
 			"BIOS", "ME", "GbE", "unknown", "EC",
 		};
@@ -965,8 +1008,10 @@
 	} else {
 		if (content->ICCRIBA == 0x34)
 			return CHIPSET_300_SERIES_CANNON_POINT;
-		msg_pwarn("Unknown flash descriptor, assuming 300 series compatibility.\n");
-		return CHIPSET_300_SERIES_CANNON_POINT;
+		if (content->CSSL == 0x11)
+			return CHIPSET_500_SERIES_TIGER_POINT;
+		msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
+		return CHIPSET_500_SERIES_TIGER_POINT;
 	}
 }
 
@@ -984,6 +1029,7 @@
 
 	switch (guess) {
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_GEMINI_LAKE:
 		/* `freq_read` was repurposed, so can't check on it any more. */
 		break;
@@ -1137,6 +1183,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		if (idx == 0) {
@@ -1173,6 +1220,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		mmio_le_writel(control, spibar + PCH100_REG_FDOC);
diff --git a/ich_descriptors.h b/ich_descriptors.h
index 274d0fe..ccfa46b 100644
--- a/ich_descriptors.h
+++ b/ich_descriptors.h
@@ -95,6 +95,13 @@
 				 ICCRIBA	:8, /* ICC Reg. Init Base Addr.	(new since Sandy Bridge) */
 				 RIL		:8; /* Register Init Length	(new since Hawell) */
 		};
+		struct {	/* new since Tiger Point */
+			uint32_t		:2,
+				 CSSO		:10, /* CPU Soft Strap Offset from PMC Base */
+						:4,
+				 CSSL		:8,  /* CPU Soft Strap Length */
+						:8;
+		};
 	};
 };
 
diff --git a/ichspi.c b/ichspi.c
index d59fd3b..0b00466 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -399,6 +399,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 		break;
 	default:
 		pprint_reg(HSFS, BERASE, reg_val, ", ");
@@ -409,6 +410,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 		pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
 		pprint_reg(HSFS, WRSDIS, reg_val, ", ");
 		break;
@@ -428,6 +430,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 		_pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
 		pprint_reg(HSFC, WET, reg_val, ", ");
 		break;
@@ -1739,6 +1742,7 @@
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		num_pr			= 6;	/* Includes GPR0 */
@@ -1771,6 +1775,7 @@
 		num_freg = 12;	/* 12 MMIO regs, but 16 regions in FD spec */
 		break;
 	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
 		num_freg = 16;
@@ -1867,6 +1872,7 @@
 		case CHIPSET_100_SERIES_SUNRISE_POINT:
 		case CHIPSET_C620_SERIES_LEWISBURG:
 		case CHIPSET_300_SERIES_CANNON_POINT:
+		case CHIPSET_500_SERIES_TIGER_POINT:
 		case CHIPSET_APOLLO_LAKE:
 		case CHIPSET_GEMINI_LAKE:
 			tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
@@ -1942,6 +1948,7 @@
 			case CHIPSET_100_SERIES_SUNRISE_POINT:
 			case CHIPSET_C620_SERIES_LEWISBURG:
 			case CHIPSET_300_SERIES_CANNON_POINT:
+			case CHIPSET_500_SERIES_TIGER_POINT:
 			case CHIPSET_APOLLO_LAKE:
 			case CHIPSET_GEMINI_LAKE:
 			case CHIPSET_BAYTRAIL:
@@ -1975,6 +1982,7 @@
 			case CHIPSET_100_SERIES_SUNRISE_POINT:
 			case CHIPSET_C620_SERIES_LEWISBURG:
 			case CHIPSET_300_SERIES_CANNON_POINT:
+			case CHIPSET_500_SERIES_TIGER_POINT:
 			case CHIPSET_APOLLO_LAKE:
 			case CHIPSET_GEMINI_LAKE:
 				break;
@@ -2007,7 +2015,8 @@
 
 		if (ich_spi_mode == ich_auto &&
 		    (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
-		     ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) {
+		     ich_gen == CHIPSET_300_SERIES_CANNON_POINT ||
+		     ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) {
 			msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
 			ich_spi_mode = ich_hwseq;
 		}
diff --git a/programmer.h b/programmer.h
index 8b21cfa..15484c1 100644
--- a/programmer.h
+++ b/programmer.h
@@ -354,6 +354,7 @@
 	CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
 	CHIPSET_C620_SERIES_LEWISBURG,
 	CHIPSET_300_SERIES_CANNON_POINT,
+	CHIPSET_500_SERIES_TIGER_POINT,
 	CHIPSET_APOLLO_LAKE,
 	CHIPSET_GEMINI_LAKE,
 };
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index 8b0bc08..890f26c 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -136,6 +136,7 @@
 "\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n"
 "\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n"
 "\t- \"400\" or \"comet\" for Intel's 400 series chipsets.\n"
+"\t- \"500\" or \"tiger\" for Intel's 500 series chipsets.\n"
 "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n"
 "the GbE blob that is required to initialize the GbE are also dumped to files.\n",
 	argv[0], argv[0]);
@@ -229,6 +230,9 @@
 			 (strcmp(csn, "400") == 0) ||
 			 (strcmp(csn, "comet") == 0))
 			cs = CHIPSET_300_SERIES_CANNON_POINT;
+		else if ((strcmp(csn, "500") == 0) ||
+			 (strcmp(csn, "tiger") == 0))
+			cs = CHIPSET_500_SERIES_TIGER_POINT;
 		else if (strcmp(csn, "apollo") == 0)
 			cs = CHIPSET_APOLLO_LAKE;
 		else if (strcmp(csn, "gemini") == 0)