diff --git a/Makefile b/Makefile
index 9eaf8d3..81a4b11 100644
--- a/Makefile
+++ b/Makefile
@@ -138,7 +138,7 @@
 else
 override CONFIG_PONY_SPI = no
 endif
-# Dediprog and FT2232 are not supported under DOS (missing USB support).
+# Dediprog, USB-Blaster and FT2232 are not supported under DOS (missing USB support).
 ifeq ($(CONFIG_DEDIPROG), yes)
 UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes
 else
@@ -277,7 +277,7 @@
 else
 override CONFIG_PONY_SPI = no
 endif
-# Dediprog and FT2232 are not supported with libpayload (missing libusb support)
+# Dediprog, USB-Blaster and FT2232 are not supported with libpayload (missing libusb support)
 ifeq ($(CONFIG_DEDIPROG), yes)
 UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes
 else
@@ -914,6 +914,7 @@
 endif
 
 define FTDI_TEST
+#include <stdlib.h>
 #include <ftdi.h>
 struct ftdi_context *ftdic = NULL;
 int main(int argc, char **argv)
diff --git a/board_enable.c b/board_enable.c
index 456e206..66c587e 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -2377,7 +2377,7 @@
 	{0x8086, 0x27b8, 0x1043, 0x2a22,  0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$",  NULL, NULL,           P3, "ASUS",        "P5LP-LE (Epson OEM)",   0,   OK, intel_ich_gpio34_raise},
 	{0x8086, 0x27da, 0x1043, 0x8179,  0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$",    NULL, NULL,           P3, "ASUS",        "P5LD2",                 0,   OK, intel_ich_gpio16_raise},
 	{0x8086, 0x27da, 0x1043, 0x8179,  0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL,           P3, "ASUS",        "P5LD2-MQ",              0,   OK, intel_ich_gpio16_raise},
-	{0x8086, 0x27da, 0x1043, 0x8179,  0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL,           P3, "ASUS",        "P5LD2-VM",              0,   NT, intel_ich_gpio16_raise},
+	{0x8086, 0x27da, 0x1043, 0x8179,  0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL,           P3, "ASUS",        "P5LD2-VM",              0,   OK, intel_ich_gpio16_raise},
 	{0x8086, 0x27b0, 0x1043, 0x8179,  0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL,        P3, "ASUS",        "P5LD2-VM DH",           0,   OK, intel_ich_gpio16_raise},
 	{0x10DE, 0x0030, 0x1043, 0x818a,  0x8086, 0x100E, 0x1043, 0x80EE, NULL,         NULL, NULL,           P3, "ASUS",        "P5ND2-SLI Deluxe",      0,   OK, nvidia_mcp_gpio10_raise},
 	{0x10DE, 0x0260, 0x1043, 0x81BC,  0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$",    NULL, NULL,           P3, "ASUS",        "P5N-D",                 0,   OK, it8718f_gpio63_raise},
@@ -2427,6 +2427,7 @@
 	{0x8086, 0x1E22, 0x17AA, 0x21F6,  0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL,       P2, "IBM/Lenovo",  "ThinkPad T530",         0,   OK, p2_whitelist_laptop},
 	{0x8086, 0x27a0, 0x17aa, 0x2015,  0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL,        P2, "IBM/Lenovo",  "ThinkPad T60",          0,   OK, p2_whitelist_laptop},
 	{0x8086, 0x27a0, 0x17aa, 0x2017,  0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL,        P2, "IBM/Lenovo",  "ThinkPad T60(s)",       0,   OK, p2_whitelist_laptop},
+	{0x8086, 0x2917, 0x17AA, 0x20F5,  0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200$", NULL, NULL,      P2, "IBM/Lenovo",  "ThinkPad X200",         0,   OK, p2_whitelist_laptop},
 	{0x8086, 0x3B07, 0x17AA, 0x2166,  0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL,         P2, "IBM/Lenovo",  "ThinkPad X201",         0,   OK, p2_whitelist_laptop},
 	{0x8086, 0x1E22, 0x17AA, 0x21FA,  0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL,       P2, "IBM/Lenovo",  "ThinkPad X230",         0,   OK, p2_whitelist_laptop},
 	{0x8086, 0x27A0, 0x17AA, 0x2017,  0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL,        P2, "IBM/Lenovo",  "ThinkPad X60(s)",       0,   OK, p2_whitelist_laptop},
diff --git a/chipset_enable.c b/chipset_enable.c
index dd4e0ea..89171b7 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -451,7 +451,7 @@
 			fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
 			rmmio_writel(fwh_idsel, ilb + fwh_sel1);
 		} else {
-			fwh_idsel_old = pci_read_long(dev, fwh_sel1) << 16;
+			fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
 			rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
 			if (fwh_sel2 > 0) {
 				fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
@@ -1593,7 +1593,7 @@
 	{0x1166, 0x0205, OK,  "Broadcom", "HT-1000",			enable_flash_ht1000},
 	{0x17f3, 0x6030, OK,  "RDC", "R8610/R3210",			enable_flash_rdc_r8610},
 	{0x8086, 0x0c60, NT,  "Intel", "S12x0",				enable_flash_s12x0},
-	{0x8086, 0x0f1c, NT,  "Intel", "Bay Trail",			enable_flash_silvermont},
+	{0x8086, 0x0f1c, OK,  "Intel", "Bay Trail",			enable_flash_silvermont},
 	{0x8086, 0x0f1d, NT,  "Intel", "Bay Trail",			enable_flash_silvermont},
 	{0x8086, 0x0f1e, NT,  "Intel", "Bay Trail",			enable_flash_silvermont},
 	{0x8086, 0x0f1f, NT,  "Intel", "Bay Trail",			enable_flash_silvermont},
@@ -1635,6 +1635,7 @@
 	{0x8086, 0x1f39, NT,  "Intel", "Avoton/Rangeley",		enable_flash_silvermont},
 	{0x8086, 0x1f3a, NT,  "Intel", "Avoton/Rangeley",		enable_flash_silvermont},
 	{0x8086, 0x1f3b, NT,  "Intel", "Avoton/Rangeley",		enable_flash_silvermont},
+	{0x8086, 0x229c, NT,  "Intel", "Braswell",			enable_flash_silvermont},
 	{0x8086, 0x2310, NT,  "Intel", "DH89xxCC (Cave Creek)",		enable_flash_pch7},
 	{0x8086, 0x2390, NT,  "Intel", "Coleto Creek",			enable_flash_pch7},
 	{0x8086, 0x2410, OK,  "Intel", "ICH",				enable_flash_ich0},
@@ -1730,42 +1731,47 @@
 	{0x8086, 0x8c5d, NT,  "Intel", "Lynx Point",			enable_flash_pch8},
 	{0x8086, 0x8c5e, NT,  "Intel", "Lynx Point",			enable_flash_pch8},
 	{0x8086, 0x8c5f, NT,  "Intel", "Lynx Point",			enable_flash_pch8},
+	{0x8086, 0x8cc1, NT,  "Intel", "9 Series",			enable_flash_pch9},
+	{0x8086, 0x8cc2, NT,  "Intel", "9 Series Engineering Sample",	enable_flash_pch9},
+	{0x8086, 0x8cc3, NT,  "Intel", "9 Series",			enable_flash_pch9},
+	{0x8086, 0x8cc4, NT,  "Intel", "Z97",				enable_flash_pch9},
+	{0x8086, 0x8cc6, NT,  "Intel", "H97",				enable_flash_pch9},
+	{0x8086, 0x8d40, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d41, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d42, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d43, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d44, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d45, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d46, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d47, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d48, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d49, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d4a, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d4b, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d4c, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d4d, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d4e, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d4f, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d50, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d51, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d52, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d53, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d54, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d55, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d56, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d57, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d58, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d59, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d5a, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d5b, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d5c, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d5d, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d5e, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
+	{0x8086, 0x8d5f, NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
 	{0x8086, 0x9c41, NT,  "Intel", "Lynx Point LP Eng. Sample",	enable_flash_pch8_lp},
 	{0x8086, 0x9c43, NT,  "Intel", "Lynx Point LP Premium",		enable_flash_pch8_lp},
 	{0x8086, 0x9c45, NT,  "Intel", "Lynx Point LP Mainstream",	enable_flash_pch8_lp},
 	{0x8086, 0x9c47, NT,  "Intel", "Lynx Point LP Value",		enable_flash_pch8_lp},
- 	{0x8086, 0x8d40, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d41, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d42, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d43, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d44, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d45, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d46, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d47, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d48, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d49, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d4a, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d4b, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d4c, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d4d, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d4e, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d4f, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d50, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d51, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d52, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d53, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d54, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d55, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d56, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d57, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d58, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d59, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d5a, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d5b, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d5c, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d5d, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d5e, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
- 	{0x8086, 0x8d5f, NT,  "Intel", "Wellsburg",			enable_flash_pch8_wb},
 	{0x8086, 0x9cc1, NT,  "Intel", "Haswell U Sample",		enable_flash_pch9},
 	{0x8086, 0x9cc2, NT,  "Intel", "Broadwell U Sample",		enable_flash_pch9},
 	{0x8086, 0x9cc3, NT,  "Intel", "Broadwell U Premium",		enable_flash_pch9},
@@ -1807,10 +1813,10 @@
 		msg_pdbg(" with PCI ID %04x:%04x",
 			 chipset_enables[i].vendor_id,
 			 chipset_enables[i].device_id);
-		msg_pinfo(". ");
+		msg_pinfo(".\n");
 
 		if (chipset_enables[i].status == NT) {
-			msg_pinfo("\nThis chipset is marked as untested. If "
+			msg_pinfo("This chipset is marked as untested. If "
 				  "you are using an up-to-date version\nof "
 				  "flashrom *and* were (not) able to "
 				  "successfully update your firmware with it,\n"
diff --git a/dediprog.c b/dediprog.c
index 4248499..851dbae 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -19,6 +19,7 @@
 
 #include "platform.h"
 
+#include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
 #include <limits.h>
diff --git a/flash.h b/flash.h
index 5fb743d..2c2839f 100644
--- a/flash.h
+++ b/flash.h
@@ -107,7 +107,6 @@
 
 /* Feature bits used for non-SPI only */
 #define FEATURE_REGISTERMAP	(1 << 0)
-#define FEATURE_BYTEWRITES	(1 << 1)
 #define FEATURE_LONG_RESET	(0 << 4)
 #define FEATURE_SHORT_RESET	(1 << 4)
 #define FEATURE_EITHER_RESET	FEATURE_LONG_RESET
diff --git a/flashchips.c b/flashchips.c
index 86546d7..4f36e95 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -1276,7 +1276,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enhance (sic!) */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -1449,7 +1449,7 @@
 		.total_size	= 512,
 		.page_size	= 256,
 		.feature_bits	= FEATURE_WRSR_WREN,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -2173,7 +2173,7 @@
 		.total_size	= 2048,
 		.page_size	= 256,
 		.feature_bits	= FEATURE_WRSR_WREN,
-		.tested		= TEST_OK_PR,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -2435,7 +2435,7 @@
 		/* does not support EWSR nor WREN and has no writable status register bits whatsoever */
 		/* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */
 		.feature_bits	= FEATURE_OTP,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_at45db,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -2772,7 +2772,7 @@
 		/* does not support EWSR nor WREN and has no writable status register bits whatsoever */
 		/* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */
 		.feature_bits	= FEATURE_OTP,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_at45db,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -4220,7 +4220,7 @@
 		.total_size	= 512,
 		.page_size	= 256,
 		.feature_bits	= FEATURE_WRSR_WREN,
-		.tested		= TEST_OK_PROBE,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -4325,7 +4325,7 @@
 		.total_size	= 4096,
 		.page_size	= 256,
 		.feature_bits	= FEATURE_WRSR_WREN,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -4619,7 +4619,7 @@
 		/* OTP: 512B total; enter 0x3A */
 		/* QPI enable 0x38, disable 0xFF */
 		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
-		.tested		= TEST_OK_PR,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -5583,7 +5583,7 @@
 		.total_size	= 256,
 		.page_size	= 256,
 		.feature_bits	= FEATURE_WRSR_WREN,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -6727,7 +6727,7 @@
 
 	{
 		.vendor		= "Macronix",
-		.name		= "MX25L2005(C)",
+		.name		= "MX25L2005(C)/MX25L2006E",
 		.bustype	= BUS_SPI,
 		.manufacture_id	= MACRONIX_ID,
 		.model_id	= MACRONIX_MX25L2005,
@@ -6765,7 +6765,7 @@
 
 	{
 		.vendor		= "Macronix",
-		.name		= "MX25L4005(A/C)",
+		.name		= "MX25L4005(A/C)/MX25L4006E",
 		.bustype	= BUS_SPI,
 		.manufacture_id	= MACRONIX_ID,
 		.model_id	= MACRONIX_MX25L4005,
@@ -6803,7 +6803,7 @@
 
 	{
 		.vendor		= "Macronix",
-		.name		= "MX25L8005/MX25V8005",
+		.name		= "MX25L8005/MX25L8006E/MX25V8005",
 		.bustype	= BUS_SPI,
 		.manufacture_id	= MACRONIX_ID,
 		.model_id	= MACRONIX_MX25L8005,
@@ -6907,7 +6907,7 @@
 			},
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* MX25L1605A bp2 only */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) supported */
 		.voltage	= {2700, 3600},
@@ -6942,7 +6942,7 @@
 			},
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6: Continuously Program (CP) mode */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B), dual I/O supported */
 		.voltage	= {2700, 3600},
@@ -6978,7 +6978,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {2700, 3600},
@@ -7014,7 +7014,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {2700, 3600},
@@ -7085,7 +7085,7 @@
 			},
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6: CP mode */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and dual I/O supported */
 		.voltage	= {2700, 3600},
@@ -7124,7 +7124,7 @@
 			},
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd,
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and dual I/O supported */
 		.voltage	= {2700, 3600},
@@ -7163,7 +7163,7 @@
 			},
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd,
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and dual I/O supported */
 		.voltage	= {2700, 3600},
@@ -7199,7 +7199,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -7235,7 +7235,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 has different meanings */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -7271,7 +7271,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 for 36E is quad enable */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -7279,7 +7279,7 @@
 
 	{
 		.vendor		= "Macronix",
-		.name		= "MX25L6445E/MX25L6473E",
+		.name		= "MX25L6445E/MX25L6465E/MX25L6473E",
 		.bustype	= BUS_SPI,
 		.manufacture_id	= MACRONIX_ID,
 		.model_id	= MACRONIX_MX25L6405,
@@ -7311,7 +7311,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {2700, 3600},
@@ -7319,13 +7319,13 @@
 
 	{
 		.vendor		= "Macronix",
-		.name		= "MX25L12805(D)",
+		.name		= "MX25L12805D",
 		.bustype	= BUS_SPI,
 		.manufacture_id	= MACRONIX_ID,
-		.model_id	= MACRONIX_MX25L12805,
+		.model_id	= MACRONIX_MX25L12805D,
 		.total_size	= 16384,
 		.page_size	= 256,
-		/* MX25L12805D has 64B of OTP; enter 0xB1, exit 0xC1 */
+		/* OTP: 64B total; enter 0xB1, exit 0xC1 */
 		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP,
 		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
@@ -7347,9 +7347,49 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd,
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
-		.read		= spi_chip_read, /* MX25L12805D: Fast read (0x0B) supported */
+		.read		= spi_chip_read, /* Fast read (0x0B) supported */
+		.voltage	= {2700, 3600},
+	},
+
+	{
+		.vendor		= "Macronix",
+		.name		= "MX25L12835F/MX25L12845E/MX25L12865E",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= MACRONIX_ID,
+		.model_id	= MACRONIX_MX25L12805D,
+		.total_size	= 16384,
+		.page_size	= 256,
+		/* OTP: 512B total; enter 0xB1, exit 0xC1 */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP,
+		.tested		= TEST_OK_PREW,
+		.probe		= probe_spi_rdid,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 4096} },
+				.block_erase = spi_block_erase_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 512} },
+				.block_erase = spi_block_erase_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 256} },
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_60,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		/* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */
+		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read, /* Fast read (0x0B) supported */
 		.voltage	= {2700, 3600},
 	},
 
@@ -7364,7 +7404,7 @@
 		/* OTP: 512B total; enter 0xB1, exit 0xC1 */
 		/* QPI enable 0x35, disable 0xF5 (0xFF et al. work too) */
 		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PR,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -7388,7 +7428,7 @@
 		},
 		/* TODO: security register */
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {1650, 2000},
@@ -7430,7 +7470,7 @@
 		},
 		/* TODO: security register */
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {1650, 2000},
@@ -7472,7 +7512,7 @@
 		},
 		/* TODO: security register */
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
 		.voltage	= {1650, 2000},
@@ -8028,7 +8068,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8062,7 +8102,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_1, /* 128 */
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8091,7 +8131,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8121,7 +8161,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_1, /* 128 */
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8208,7 +8248,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8237,7 +8277,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 	},
@@ -8265,7 +8305,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8294,7 +8334,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8323,7 +8363,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8352,7 +8392,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -8381,7 +8421,7 @@
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* TODO: check */
-		.unlock		= spi_disable_blockprotect,
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 		.voltage	= {2700, 3600},
@@ -9635,7 +9675,7 @@
 		.total_size	= 64,
 		.page_size	= 256,
 		.feature_bits	= FEATURE_WRSR_WREN,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_res2, /* The continuation code is transferred as the 3rd byte m( */
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -12014,7 +12054,7 @@
 		.total_size	= 256,
 		.page_size	= 4096,
 		.feature_bits	= FEATURE_EITHER_RESET,
-		.tested		= TEST_UNTESTED,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_jedec,
 		.probe_timing	= 1,			/* 150 ns */
 		.block_erasers	=
@@ -12898,7 +12938,7 @@
 				},
 				.block_erase = erase_block_82802ab,
 			}, {
-				.eraseblocks = { {256 * 1024, 1}, },
+				.eraseblocks = { {256 * 1024, 1} },
 				.block_erase = NULL, /* Only in A/A mux mode */
 			}
 		},
@@ -13330,7 +13370,7 @@
 		/* supports SFDP */
 		/* OTP: 756B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
 		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP,
-		.tested		= TEST_OK_PR,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
diff --git a/flashchips.h b/flashchips.h
index 358fff3..1bf811a 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -27,7 +27,7 @@
 /*
  * Please keep this list sorted alphabetically by manufacturer. The first
  * entry of each section should be the manufacturer ID, followed by the
- * list of devices from that manufacturer (sorted by device IDs).
+ * list of devices from that manufacturer (sorted by device ID).
  *
  * Most LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no
  * continuation code.
@@ -303,6 +303,8 @@
 #define EON_EN29LV010		0x7F6E
 #define EON_EN29LV040		0x4F	/* Same as EN29LV040A */
 #define EON_EN29LV640B		0xCB
+#define EON_EN29LV640T		0xC9
+#define EON_EN29LV640U		0x7E
 #define EON_EN29F002T		0x7F92	/* Same as EN29F002A */
 #define EON_EN29F002B		0x7F97	/* Same as EN29F002AN */
 #define EON_EN29GL064HL		0x7E0C01	/* Uniform Sectors, WP protects Top OR Bottom sector */
@@ -466,13 +468,13 @@
  * and use the same set of IDs. */
 #define MACRONIX_MX25L512	0x2010	/* Same as MX25L512E, MX25V512, MX25V512C */
 #define MACRONIX_MX25L1005	0x2011	/* Same as MX25L1005C, MX25L1006E */
-#define MACRONIX_MX25L2005	0x2012	/* Same as MX25L2005C */
-#define MACRONIX_MX25L4005	0x2013	/* Same as MX25L4005A, MX25L4005C */
-#define MACRONIX_MX25L8005	0x2014	/* Same as MX25V8005; FIXME: MX25L8073E (4k 0x20) */
+#define MACRONIX_MX25L2005	0x2012	/* Same as MX25L2005C, MX25L2006E */
+#define MACRONIX_MX25L4005	0x2013	/* Same as MX25L4005A, MX25L4005C, MX25L4006E */
+#define MACRONIX_MX25L8005	0x2014	/* Same as MX25V8005, MX25L8006E, FIXME: MX25L8073E (4k 0x20) */
 #define MACRONIX_MX25L1605	0x2015	/* MX25L1605 (64k 0x20); MX25L1605A/MX25L1606E (4k 0x20, 64k 0x52); MX25L1605D/MX25L1608D/MX25L1673E (4k 0x20) */
 #define MACRONIX_MX25L3205	0x2016	/* MX25L3205, MX25L3205A (64k 0x20); MX25L3205D/MX25L3208D (4k 0x20); MX25L3206E (4k 0x20, 64k 0x52); MX25L3273E (4k 0x20, 32k 0x52) */
-#define MACRONIX_MX25L6405	0x2017	/* MX25L6405, MX25L6405D (64k 0x20); MX25L6406E/MX25L6436E (4k 0x20); MX25L6445E/MX25L6473E (4k 0x20, 32k 0x52) */
-#define MACRONIX_MX25L12805	0x2018	/* Same as MX25L12805D, MX25L12835F, MX25L12845E (the latter two support completely new ID commands) */
+#define MACRONIX_MX25L6405	0x2017	/* MX25L6405, MX25L6405D (64k 0x20); MX25L6406E/MX25L6436E (4k 0x20); MX25L6445E/MX25L6465E/MX25L6473E (4k 0x20, 32k 0x52) */
+#define MACRONIX_MX25L12805D	0x2018	/* MX25L12805D (no 32k); MX25L12865E, MX25L12835F, MX25L12845E (32k 0x52) */
 #define MACRONIX_MX25L25635F	0x2019	/* Same as MX25L25639F, but the latter seems to not support REMS */
 #define MACRONIX_MX25L1635D	0x2415
 #define MACRONIX_MX25L1635E	0x2515	/* MX25L1635{E} */
@@ -784,6 +786,48 @@
 #define ST_M29W010B		0x23
 #define ST_M29W040B		0xE3
 #define ST_M29W512B		0x27
+#define ST_M28W160ECB		0x88CF
+#define ST_M28W160ECT		0x88CE
+#define ST_M28W320FCB		0x88BB
+#define ST_M28W320FCT		0x88BA
+#define ST_M28W640HCB		0x8849
+#define ST_M28W640HCT		0x8848
+#define ST_M29DW127G		0x7E2004
+#define ST_M29W128GH		0x7E2101
+#define ST_M29W128GL		0x7E2100
+#define ST_M29W160EB		0x2249
+#define ST_M29W160ET		0x22C4
+#define ST_M29W256GH		0x7E21xx
+#define ST_M29W256GL		0x7E21xx
+#define ST_M29W320DB		0x88CB
+#define ST_M29W320DT		0x88CA
+#define ST_M29W400FB		0x00EF
+#define ST_M29W400FT		0x00EE
+#define ST_M29W512GH		0x7E2301
+#define ST_M29W640FB		0x22FD
+#define ST_M29W640FT		0x22ED
+#define ST_M29W640GB		0x7E1000
+#define ST_M29W640GH		0x7E0C01
+#define ST_M29W640GL		0x7E0C00
+#define ST_M29W640GT		0x7E1001
+#define ST_M29W800FB		0x225B
+#define ST_M29W800FT		0x22D7
+#define ST_M58BW16FB		0x8839
+#define ST_M58BW16FT		0x883A
+#define ST_M58BW32FB		0x8837
+#define ST_M58BW32FT		0x8838
+#define ST_M58WR016KB		0x8813
+#define ST_M58WR016KT		0x8812
+#define ST_M58WR032KB		0x8815
+#define ST_M58WR032KT		0x8814
+#define ST_M58WR064KB		0x8811
+#define ST_M58WR064KT		0x8810
+#define ST_MT28GU01G___1	0x88B0
+#define ST_MT28GU01G___2	0x88B1
+#define ST_MT28GU256___1	0x8901
+#define ST_MT28GU256___2	0x8904
+#define ST_MT28GU512___1	0x887E
+#define ST_MT28GU512___2	0x8881
 #define ST_N25Q016__1E		0xBB15	/* N25Q016, 1.8V, (uniform sectors expected) */
 #define ST_N25Q032__3E		0xBA16	/* N25Q032, 3.0V, (uniform sectors expected) */
 #define ST_N25Q032__1E		0xBB16	/* N25Q032, 1.8V, (uniform sectors expected) */
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index 5d08ea3..799d5b9 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -1094,6 +1094,8 @@
 .br
 Joshua Roys
 .br
+Ky\[:o]sti M\[:a]lkki
+.br
 Luc Verhaegen
 .br
 Li-Ta Lo
@@ -1140,7 +1142,7 @@
 .br
 some others, please see the flashrom svn changelog for details.
 .br
-All authors can be reached via email at <flashrom@flashrom.org>.
+All still active authors can be reached via email at <flashrom@flashrom.org>.
 .PP
 This manual page was written by Uwe Hermann <uwe@hermann-uwe.de>,
 Carl-Daniel Hailfinger and others.
diff --git a/flashrom.c b/flashrom.c
index 9df1478..e58f707 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -2020,7 +2020,7 @@
 	// ////////////////////////////////////////////////////////////
 
 	if (write_it && erase_and_write_flash(flash, oldcontents, newcontents)) {
-		msg_cerr("Uh oh. Erase/write failed.");
+		msg_cerr("Uh oh. Erase/write failed. ");
 		if (read_all_first) {
 			msg_cerr("Checking if anything has changed.\n");
 			msg_cinfo("Reading current flash chip contents... ");
diff --git a/ichspi.c b/ichspi.c
index 0cd9c68..1e3f62a 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1195,7 +1195,7 @@
 	struct block_eraser *eraser;
 
 	total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
-	msg_cdbg("Found %d attached SPI flash chip",
+	msg_cdbg("Hardware sequencing reports %d attached SPI flash chip",
 		 (hwseq_data.size_comp1 != 0) ? 2 : 1);
 	if (hwseq_data.size_comp1 != 0)
 		msg_cdbg("s with a combined");
@@ -1210,14 +1210,14 @@
 	erase_size_high = ich_hwseq_get_erase_block_size(boundary);
 
 	if (boundary == 0) {
-		msg_cdbg("There is only one partition containing the whole "
+		msg_cdbg2("There is only one partition containing the whole "
 			 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
 		eraser->eraseblocks[0].size = erase_size_high;
 		eraser->eraseblocks[0].count = size_high / erase_size_high;
-		msg_cdbg("There are %d erase blocks with %d B each.\n",
+		msg_cdbg2("There are %d erase blocks with %d B each.\n",
 			 size_high / erase_size_high, erase_size_high);
 	} else {
-		msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided "
+		msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
 			 "at address 0x%06x in two partitions.\n",
 			 0, total_size-1, boundary);
 		size_low = total_size - size_high;
diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c
index 2d6def1..b5d4202 100644
--- a/nicintel_eeprom.c
+++ b/nicintel_eeprom.c
@@ -275,7 +275,7 @@
 	.erase = nicintel_ee_erase,
 };
 
-static int nicintel_spi_shutdown(void *eecp)
+static int nicintel_ee_shutdown(void *eecp)
 {
 	uint32_t old_eec = *(uint32_t *)eecp;
 	/* Request bitbanging and unselect the chip first to be safe. */
@@ -323,7 +323,7 @@
 			return 1;
 		*eecp = eec;
 
-		if (register_shutdown(nicintel_spi_shutdown, eecp))
+		if (register_shutdown(nicintel_ee_shutdown, eecp))
 			return 1;
 	}
 
diff --git a/print.c b/print.c
index 7528e32..59bc455 100644
--- a/print.c
+++ b/print.c
@@ -141,7 +141,7 @@
 		msg_ginfo(" ");
 	msg_gdbg("range [V]");
 	msg_ginfo("\n\n");
-	msg_ginfo("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n");
+	msg_ginfo("(P = PROBE, R = READ, E = ERASE, W = WRITE, - = N/A)\n\n");
 
 	for (chip = flashchips; chip->name != NULL; chip++) {
 		/* Don't print generic entries. */
@@ -403,12 +403,14 @@
 		for (i = 0; i < maxboardlen - strlen(b->name); i++)
 			msg_ginfo(" ");
 
-		if (b->working == OK)
-			msg_ginfo("OK      ");
-		else if (b->working == NT)
-			msg_ginfo("NT      ");
-		else
-			msg_ginfo("BAD     ");
+		switch (b->working) {
+		case OK:  msg_ginfo("OK      "); break;
+		case NT:  msg_ginfo("NT      "); break;
+		case DEP: msg_ginfo("DEP     "); break;
+		case NA:  msg_ginfo("N/A     "); break;
+		case BAD:
+		default:  msg_ginfo("BAD     "); break;
+		}
 
 		for (e = board_matches; e->vendor_name != NULL; e++) {
 			if (strcmp(e->vendor_name, b->vendor)
@@ -548,7 +550,8 @@
 	B("Albatron",	"PM266A Pro",		OK, "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview&no=56", NULL), /* FIXME */
 	B("Alienware",	"Aurora-R2",		BAD, NULL, "Mainboard model is 0RV30W. Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."),
 	B("AOpen",	"i945GMx-VFX",		OK, NULL, "This is (also?) an OEM board from FSC (used in e.g. ESPRIMO Q5010 with designation D2544-B1)."),
-	B("AOpen",	"vKM400Am-S",		OK, "http://usa.aopen.com/products_detail.aspx?Auno=824", NULL),
+	B("AOpen",	"UK79G-1394",		OK, "http://global.aopen.com/products_detail.aspx?auno=9", "Used in EZ18 barebones"),
+	B("AOpen",	"vKM400Am-S",		OK, "http://global.aopen.com/products_detail.aspx?Auno=824", NULL),
 	B("Artec Group","DBE61",		OK, "http://wiki.thincan.org/DBE61", NULL),
 	B("Artec Group","DBE62",		OK, "http://wiki.thincan.org/DBE62", NULL),
 	B("ASI",	"MB-5BLMP",		OK, "http://www.hojerteknik.com/winnet.htm", "Used in the IGEL WinNET III thin client."),
@@ -644,6 +647,7 @@
 	B("ASUS",	"M4A89GTD PRO",		OK, "http://www.asus.com/Motherboards/AMD_AM3/M4A89GTD_PRO/", NULL),
 	B("ASUS",	"M4N68T V2",		OK, "http://www.asus.com/Motherboards/AMD_AM3/M4N68T_V2/", NULL),
 	B("ASUS",	"M4N78 PRO",		OK, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4N78_PRO/", NULL),
+	B("ASUS",	"M4N78 SE",		OK, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4N78_SE/", NULL),
 	B("ASUS",	"M5A78L-M LX",		OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/M5A78LM_LX/", "The MAC address of the onboard LAN NIC is stored in flash, hence overwritten by flashrom; see http://www.flashrom.org/pipermail/flashrom/2012-May/009200.html"),
 	B("ASUS",	"M5A97 (rev. 1.0)",	OK, "http://www.asus.com/Motherboard/M5A97/", NULL),
 	B("ASUS",	"M5A99X EVO",		OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/", NULL),
@@ -698,7 +702,7 @@
 	B("ASUS",	"P5L-VM 1394",		OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL),
 	B("ASUS",	"P5LD2",		OK, NULL, NULL),
 	B("ASUS",	"P5LD2-MQ",		OK, "http://support.asus.com/download.aspx?SLanguage=en&p=8&s=12&m=Vintage-PH2&os=&hashedid=n/a", "Found in ASUS Vintage-PH2 barebones."),
-	B("ASUS",	"P5LD2-VM",		NT, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM/", "Untested board enable."),
+	B("ASUS",	"P5LD2-VM",		OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM/", NULL),
 	B("ASUS",	"P5LD2-VM DH",		OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM_DH/", NULL),
 	B("ASUS",	"P5LP-LE (Lithium-UL8E)", OK, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00379616&tmp_task=prodinfoCategory&cc=us&dlc=en&lc=en&product=1159887", "This is an OEM board from HP."),
 	B("ASUS",	"P5LP-LE (Epson OEM)",	OK, NULL, "This is an OEM board from Epson (e.g. Endeavor MT7700)."),
@@ -824,6 +828,8 @@
 	B("GIGABYTE",	"GA-965GM-S2 (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL),
 	B("GIGABYTE",	"GA-965P-DS4",		OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL),
 	B("GIGABYTE",	"GA-970A-D3P (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4642", NULL),
+	B("GIGABYTE",	"GA-970A-UD3P (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=5194", "Primary flash chip is a Macronix MX25L3206E."),
+	B("GIGABYTE",	"GA-990FXA-UD3 (rev. 4.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4672", NULL),
 	B("GIGABYTE",	"GA-A75M-UD2H",		OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3928", NULL),
 	B("GIGABYTE",	"GA-B85M-D3H",		OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4567", NULL),
 	B("GIGABYTE",	"GA-EP31-DS3L (rev. 2.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2964", NULL),
@@ -833,6 +839,7 @@
 	B("GIGABYTE",	"GA-H61M-D2-B3",	OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3773", NULL),
 	B("GIGABYTE",	"GA-H61M-D2H-USB3",	OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4004", NULL),
 	B("GIGABYTE",	"GA-H77-D3H",		OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4141", "Does only work with -p internal:ich_spi_mode=hwseq due to an evil twin of MX25L6405 and ICH SPI lockdown."),
+	B("GIGABYTE",	"GA-H77-DS3H (rev. 1.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4318", NULL),
 	B("GIGABYTE",	"GA-H77M-D3H",		OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4388", NULL),
 	B("GIGABYTE",	"GA-K8N51GMF-9",	OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL),
 	B("GIGABYTE",	"GA-K8N51GMF",		OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL),
@@ -853,6 +860,7 @@
 	B("GIGABYTE",	"GA-MA790FX-DQ6",	OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL),
 	B("GIGABYTE",	"GA-MA790GP-DS4H",	OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL),
 	B("GIGABYTE",	"GA-MA790XT-UD4P (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL),
+	B("GIGABYTE",	"GA-P55-USB3 (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3440", NULL),
 	B("GIGABYTE",	"GA-P55A-UD4 (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL),
 	B("GIGABYTE",	"GA-P55A-UD7"		, OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3324", NULL),
 	B("GIGABYTE",	"GA-P67A-UD3P",		OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3649", NULL),
@@ -975,6 +983,7 @@
 	B("MSI",	"MS-7756 (H77MA-G43)",	OK, "http://www.msi.com/product/mb/H77MA-G43.html", NULL),
 	B("MSI",	"MS-7808 (B75MA-E33)",	OK, "http://www.msi.com/product/mb/B75MA-E33.html", NULL),
 	B("MSI",	"MS-7816 (H87-G43)",	OK, "http://www.msi.com/product/mb/H87-G43.html", NULL),
+	B("MSI",	"MS-7817 (H81M-E33)",	OK, "http://www.msi.com/product/mb/H81ME33.html", NULL),
 	B("MSI",	"MS-9830 (IM-945GSE-A, A9830IMS)", OK, "http://www.msi.com/product/ipc/IM-945GSE-A.html", NULL),
 	B("NEC",	"PowerMate 2000",	OK, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL),
 	B("Nokia",	"IP530",		OK, NULL, NULL),
@@ -1131,7 +1140,7 @@
 	B("IBM/Lenovo",	"ThinkPad T420",	BAD, "http://www.thinkwiki.org/wiki/Category:T420", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
 	B("IBM/Lenovo",	"ThinkPad T410s",	BAD, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25X64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
 	B("IBM/Lenovo",	"ThinkPad X1",		BAD, "http://www.thinkwiki.org/wiki/Category:X1", "Probing works (ST M25PX64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."),
-	B("IBM/Lenovo",	"ThinkPad T530",	OK, "http://www.thinkwiki.org/wiki/Category:T530", "Works fine but only with coreboot (due to locked regions and additional PR restrictions)."),
+	B("IBM/Lenovo",	"ThinkPad T530",	DEP, "http://www.thinkwiki.org/wiki/Category:T530", "Works fine but only with coreboot (due to locked regions and additional PR restrictions)."),
 	B("IBM/Lenovo",	"ThinkPad 240",		BAD, "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later."),
 	B("IBM/Lenovo",	"3000 V100 TF05Cxx",	OK, "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3000Notebook&series=Lenovo+3000+V+Series#viewallmodelstop", NULL),
 	//B("MSI",	"GT60-2OD",		OK, "http://www.msi.com/product/nb/GT60_2OD.html", NULL), requires layout patches
diff --git a/programmer.c b/programmer.c
index fd634b2..1b27c3c 100644
--- a/programmer.c
+++ b/programmer.c
@@ -119,7 +119,7 @@
 int registered_master_count = 0;
 
 /* This function copies the struct registered_master parameter. */
-int register_master(struct registered_master *mst)
+int register_master(const struct registered_master *mst)
 {
 	if (registered_master_count >= MASTERS_MAX) {
 		msg_perr("Tried to register more than %i master "
diff --git a/programmer.h b/programmer.h
index f82e950..c61f429 100644
--- a/programmer.h
+++ b/programmer.h
@@ -321,8 +321,6 @@
 #define SUPERIO_VENDOR_WINBOND	0x2
 #endif
 #if NEED_PCI == 1
-struct pci_filter;
-struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
 struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass);
 struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
 struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
@@ -691,7 +689,7 @@
 };
 extern struct registered_master registered_masters[];
 extern int registered_master_count;
-int register_master(struct registered_master *mst);
+int register_master(const struct registered_master *mst);
 
 /* serprog.c */
 #if CONFIG_SERPROG == 1
diff --git a/sb600spi.c b/sb600spi.c
index 69fad65..37ecfd9 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -141,7 +141,7 @@
 		} else if (rev == 0x16) {
 			amd_gen = CHIPSET_BOLTON;
 			msg_pdbg("Bolton detected.\n");
-		} else if (rev >= 0x39 && rev <= 0x3A) {
+		} else if ((rev >= 0x39 && rev <= 0x3A) || rev == 0x42) {
 			amd_gen = CHIPSET_YANGTZE;
 			msg_pdbg("Yangtze detected.\n");
 		} else {
@@ -498,7 +498,7 @@
 	free(arg);
 
 	/* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at
-	 * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50: Misc_Reg: 80h-87h;
+	 * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50, Bolton: Misc_Reg: 80h-87h;
 	 * sb7xx, sp5100: PM_Reg: B0h-B1h) etc. */
 	uint8_t reg = pci_read_byte(dev, 0x40);
 	if ((reg & (1 << 7)) == 0) {
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 69b2126..bf63fb3 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -260,7 +260,7 @@
 	/* Fall through. */
 	case 4:
 		msg_cdbg("Chip status register: Block Protect 4 (BP4) is %sset\n",
-			 (status & (1 << 5)) ? "" : "not ");
+			 (status & (1 << 6)) ? "" : "not ");
 	case 3:
 		msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n",
 			 (status & (1 << 5)) ? "" : "not ");