tree d749b21ab64b5d12af4f22f5e0fb214d890111e8
parent 76c2887154d00fc3350bd27ca9f14c5f38ce0fca
author Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> 1226968862 +0000
committer Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> 1226968862 +0000

Check for failed SPI command execution

Although SPI itself does not have a mechanism to signal command failure,
the SPI host may be unable to send a given command over the wire due
to security or hardware limitations. The current code ignores these
mechanisms completely and simply assumes almost every command succeeds.
Complain if SPI command execution fails.

Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.

Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.

Corresponding to flashrom svn r345 and coreboot v2 svn r3757.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>