tree 3b1c6092c3b9c501cba4600946725edc4399275a
parent 885917c1594fa68ddbf5213099d99167105c046b
author Sergii Dmytruk <sergii.dmytruk@3mdeb.com> 1636322712 +0200
committer Nico Huber <nico.h@gmx.de> 1672936501 +0000

dummyflasher: add SR2 and SR3 emulation harness

Prepare everything for emulating SR2 and SR3 for chips that have it.

This is needed for accessing SRP1 and WPS bits which are involved in
write protection. The emulated register doesn't affect anything yet
and will be tested by write-protection tests.

Tested: check how input value affects status registers of emulated chip

flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 |
        grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 |
        grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 |
        grep 'Initial status register'

Mind that at this point there are no chips that emulate more than one
status register.

Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59072
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71457
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>