flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8
There are two competing sets of instructions to access the extended
address register of 4BA SPI chips. Some chips even support both sets.
To prepare for other instructions than the default 0xc5/0xc8, rename
the original feature flag.
Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c
Ticket: https://ticket.coreboot.org/issues/357
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635
Original-Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70992
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/dediprog.c b/dediprog.c
index bacb6b8..abd0e0f 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -408,7 +408,7 @@
}
}
} else {
- if (flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR) {
+ if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) {
if (spi_set_extended_address(flash, start >> 24))
return 1;
} else if (start >> 24) {
diff --git a/flash.h b/flash.h
index c77522d..29da202 100644
--- a/flash.h
+++ b/flash.h
@@ -127,16 +127,17 @@
#define FEATURE_4BA_ENTER (1 << 10) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN */
#define FEATURE_4BA_ENTER_WREN (1 << 11) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN */
#define FEATURE_4BA_ENTER_EAR7 (1 << 12) /**< Can enter/exit 4BA mode by setting bit7 of the ext addr reg */
-#define FEATURE_4BA_EXT_ADDR (1 << 13) /**< Regular 3-byte operations can be used by writing the most
- significant address byte into an extended address register. */
+#define FEATURE_4BA_EAR_C5C8 (1 << 13) /**< Regular 3-byte operations can be used by writing the most
+ significant address byte into an extended address register
+ (using 0xc5/0xc8 instructions). */
#define FEATURE_4BA_READ (1 << 14) /**< Native 4BA read instruction (0x13) is supported. */
#define FEATURE_4BA_FAST_READ (1 << 15) /**< Native 4BA fast read instruction (0x0c) is supported. */
#define FEATURE_4BA_WRITE (1 << 16) /**< Native 4BA byte program (0x12) is supported. */
/* 4BA Shorthands */
#define FEATURE_4BA_NATIVE (FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE)
-#define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE)
-#define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE)
-#define FEATURE_4BA_EAR7 (FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE)
+#define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE)
+#define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE)
+#define FEATURE_4BA_EAR7 (FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE)
/*
* Most flash chips are erased to ones and programmed to zeros. However, some
* other flash chips, such as the ENE KB9012 internal flash, work the opposite way.
diff --git a/flashchips.c b/flashchips.c
index c398536..736f1b3 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -17403,7 +17403,7 @@
/* supports SFDP */
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN |
- FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ |
+ FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ |
FEATURE_WRSR2,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
diff --git a/spi25.c b/spi25.c
index 60ddb96..d147dbb 100644
--- a/spi25.c
+++ b/spi25.c
@@ -376,7 +376,7 @@
cmd_buf[4] = (addr >> 0) & 0xff;
return 4;
} else {
- if (flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR) {
+ if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) {
if (spi_set_extended_address(flash, addr >> 24))
return -1;
} else if (addr >> 24) {