)]}'
{
  "commit": "512059118e9ff56d2b4f3c324db5e764e288ac68",
  "tree": "7c3c384d1579b467135fd85dd9cfbb88abb4771c",
  "parents": [
    "d7c7552b4b7a94509a86404ee4bc9b0f2fdd7359"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.huber@secunet.com",
    "time": "Fri Mar 17 17:59:54 2017 +0100"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Tue Jun 20 11:47:49 2017 +0200"
  },
  "message": "Handle Intel Wildcat Point *LP* like Lynx Point LP\n\nThe subtle difference was ignored when adding these chipsets. The\nintegrated Wildcat Point LP PCH is documented in [1].\n\nI\u0027m not sure how to account for \"Broadwell H\" which seems not publicly\ndocumented. Maybe it\u0027s an unreleased HM9*, in which case the non-LP\npath should be correct.\n\n[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,\n    Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor\n    Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet\n    Revision 004\n    Document Number: 330837\n\nChange-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c\nSigned-off-by: Nico Huber \u003cnico.huber@secunet.com\u003e\nReviewed-on: https://review.coreboot.org/18883\nReviewed-by: Youness Alaoui \u003csnifikino@gmail.com\u003e\nReviewed-by: David Hendricks \u003cdavid.hendricks@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilippe.mathieu.daude@gmail.com\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
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}