)]}'
{
  "commit": "5100a8a9aed38ed96e182da22d3ed1a01202350b",
  "tree": "de0f7f28da67b7528a9b35f120fb2ffd410f66ee",
  "parents": [
    "93bb375356073782ba20a3139cfe08905f0eb4ab"
  ],
  "author": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Wed May 13 22:51:27 2009 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Wed May 13 22:51:27 2009 +0000"
  },
  "message": "Generic status register prettyprinting for SST25*\n\nEven if we don\u0027t tell the user about the areas the block locking bits\ncorrespond to, printing a detailed list of which lock bits are set is a\ndefinite improvement.\n\nCorresponding to flashrom svn r505.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\n\nSample output:\n[...]\nProbing for SST SST25VF032B, 4096 KB: RDID returned bf 25 4a.\nprobe_spi_rdid_generic: id1 0xbf, id2 0x254a\nChip status register is 1c\nChip status register: Block Protect Write Disable (BPL) is not set\nChip status register: Auto Address Increment Programming (AAI) is not\nset\nChip status register: Bit 5 / Block Protect 3 (BP3) is not set\nChip status register: Bit 4 / Block Protect 2 (BP2) is set\nChip status register: Bit 3 / Block Protect 1 (BP1) is set\nChip status register: Bit 2 / Block Protect 0 (BP0) is set\nChip status register: Write Enable Latch (WEL) is not set\nChip status register: Write In Progress (WIP/BUSY) is not set\nFound chip \"SST SST25VF032B\" (4096 KB) at physical address 0xffc00000.\n\nAcked-by: Cristi Magherusan \u003ccristi.magherusan@net.utcluj.ro\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b61f4331694749472c37f677a85a74cf1138ff6c",
      "old_mode": 33188,
      "old_path": "spi.c",
      "new_id": "6d1185e53e7ba837d25073d2a2512963a168b7c3",
      "new_mode": 33188,
      "new_path": "spi.c"
    }
  ]
}