spi25: Implement multi-i/o reads
We describe a read operation in a new `struct spi_read_op`. It's
comprised of the i/o mode, its opcode, an optional mode byte, and
the number of dummy bytes.
Based on this information about the various read operations, and
the flash and master feature flags, we select the read operation
with the highest throughput.
The following assumption is made about 4BA chips: When it supports
native-4BA fast reads and a multi-i/o version of the regular fast
read, then it should also support the respective native-4BA, multi-
i/o version (yes, JEDEC, there are too many read commands!). So far
this seems to hold for the chips in our database.
Change-Id: I3c93e71d85f769831d637c14d3571f7ddb54d8b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/49
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/include/spi_command.h b/include/spi_command.h
index 54dfe48..b0daeee 100644
--- a/include/spi_command.h
+++ b/include/spi_command.h
@@ -68,6 +68,15 @@
QPI_4_4_4,
};
+/* describes properties of a read operation */
+struct spi_read_op {
+ enum io_mode io_mode;
+ bool native_4ba;
+ uint8_t opcode;
+ uint8_t mode_byte; /* optional byte to send after the address, if != 0 */
+ uint8_t dummy_len; /* dummy bytes (including optional mode byte) */
+};
+
struct spi_command {
enum io_mode io_mode;
size_t opcode_len; /* bytes to write in opcode i/o phase */